nand_test.v

256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual

    #200;
    WE = 1'b0;
    #200;
    WE = 1'b1;          //write enable, data latched in
    #200;
  
    CLE = 1'b0;
    #200;
    ALE = 1'b1;
    IO_BUF = addr_1st;  //address cycle 1
  
    #200;
    WE = 1'b0;
    #200;
    WE = 1'b1;          //write enable, data latched in
    #200;
  
    IO_BUF = addr_2nd;  //address cycle 2
    
    #200;
    WE = 1'b0;
    #200;
    WE = 1'b1;          //write enable, data latched in
    #200;
  
    IO_BUF = addr_3rd;  //address cycle 3
  
    #200;
    WE = 1'b0;
    #200;
    WE = 1'b1;          //write enable, data latched in
    #200;
                        //address cycle 4
//    IO_BUF = addr_4th & 8'h03;
  
//    #200;
//    WE = 1'b0;
//    #200;
//    WE = 1'b1;          //write enable, data latched in
//    #200;
  
    ALE = 1'b0;
    IO_BUF = 8'hzz;     //read data from memory
    #15e3;
    if(cmd === 8'h00) temp = addr_1st;
    if(cmd === 8'h01) temp = 256 + addr_1st;
    if(cmd === 8'h50) temp = 512 + addr_1st[3:0];
    for(i=temp;i<temp+n;i=i+1)
    begin
      add_bk = U_NAND256R3A.addr_block;
      add_pg = U_NAND256R3A.addr_page;
      add_cl = U_NAND256R3A.addr_column;
      #200;
      RE = 1'b0;
      #200
      RE = 1'b1;
      $display("%t, Block[%d],  Page[%d], Column[%d], Data=[%h]",$realtime,add_bk,add_pg,add_cl,IO);
      if(((cmd === 8'h00)||(cmd === 8'h01))&&((i-527)%528 === 0)) #(10e3+200);
      if(((cmd === 8'h00)||(cmd === 8'h01))&&((i-527)%16 === 0)) #(10e3+200);
    end
  end
endtask
//#########################################################

//=========================================================
// Page Program
//=========================================================
task PROGRAM;
  input[7:0] addr_1st;
  input[7:0] addr_2nd;
  input[7:0] addr_3rd;
//  input[7:0] addr_4th;
  input[7:0] data;
  input      n;
  integer    n,i;

  begin
    #200;
    CLE = 1'b1;
    IO_BUF = 8'h80;     //command input, area a
    #200;
    WE = 1'b0;
    #200;
    WE = 1'b1;          //write enable, data latched in
    #200;
  
    CLE = 1'b0;
    #200;
    ALE = 1'b1;
    IO_BUF = addr_1st;  //address cycle 1
    #200;
    WE = 1'b0;
    #200;
    WE = 1'b1;          //write enable, data latched in
    #200;
  
    IO_BUF = addr_2nd;  //address cycle 2
    #200;
    WE = 1'b0;
    #200;
    WE = 1'b1;          //write enable, data latched in
    #200;
  
    IO_BUF = addr_3rd;  //address cycle 3
    #200;
    WE = 1'b0;
    #200;
    WE = 1'b1;          //write enable, data latched in
    #200;
                        //address cycle 4
 //   IO_BUF = addr_4th & 8'h03;
 //   #200;
 //   WE = 1'b0;
 //   #200;
 //   WE = 1'b1;          //write enable, data latched in
 //   #200;
  
    ALE = 1'b0;
  
    for(i=0;i<n;i=i+1)
    begin
      IO_BUF = data;
      #200;
      WE = 1'b0;
      #200;
      WE = 1'b1;        //write enable, data latched in
      #200;
    end
  
    CLE = 1'b1;
    IO_BUF = 8'h10;     //Confirm Code
    #200;
    WE = 1'b0;
    #200;
    WE = 1'b1;          //write enable, data latched in
    #200;
  end
endtask
//#########################################################

//=========================================================
// Copy Back Program
//=========================================================
task COPY_BACK;
  input[23:0] address_src;
  input[23:0] address_tgt;
  reg  [23:0] address_src;
  reg  [23:0] address_tgt;
  begin
	  #100;
	  CLE = 1'b1;
	  IO_BUF = 8'h00;
	  #100;
    WE = 1'b0;
    #100;
    WE = 1'b1;          //write enable, data latched in
    #100;
    
    CLE = 1'b0;
    #100;
    ALE = 1'b1;
    IO_BUF = address_src[7:0];
    #100;
    WE = 1'b0;
    #100;
    WE = 1'b1;          //write enable, data latched in
    #100;
    IO_BUF = address_src[15:8];
    #100;
    WE = 1'b0;
    #100;
    WE = 1'b1;          //write enable, data latched in
    #100;
    IO_BUF = address_src[23:16];
    #100;
    WE = 1'b0;
    #100;
    WE = 1'b1;          //write enable, data latched in
    #100;
    //IO_BUF = address_src[25:24];
    //#100;
    //WE = 1'b0;
    //#100;
    //WE = 1'b1;          //write enable, data latched in
    //#100;

    #15e3;
    ALE = 1'b0;
    #100
    CLE = 1'b1;
    IO_BUF = 8'h8A;
    #100;
    WE = 1'b0;
    #100;
    WE = 1'b1;          //write enable, data latched in
    #100;

    CLE = 1'b0;
    #100;
    ALE = 1'b1;
    IO_BUF = address_tgt[7:0];
    #100;
    WE = 1'b0;
    #100;
    WE = 1'b1;          //write enable, data latched in
    #100;
    IO_BUF = address_tgt[15:8];
    #100;
    WE = 1'b0;
    #100;
    WE = 1'b1;          //write enable, data latched in
    #100;
    IO_BUF = address_tgt[23:16];
    #100;
    WE = 1'b0;
    #100;
    WE = 1'b1;          //write enable, data latched in
    #100;
    //IO_BUF = address_tgt[25:24];
    //#100;
    //WE = 1'b0;
    //#100;
    //WE = 1'b1;          //write enable, data latched in
    //#100;

    ALE = 1'b0;
    #100
    CLE = 1'b1;
    IO_BUF = 8'h10;
    #100;
    WE = 1'b0;
    #100;
    WE = 1'b1;          //write enable, data latched in
    #100;
  end
endtask

//=========================================================
// Block Erase
//=========================================================
task BLOCK_ERASE;
  input[7:0] addr_1st;
  input[7:0] addr_2nd;
  //input[7:0] addr_3rd;

  begin
    #200;
    CLE = 1'b1;
    IO_BUF = 8'h60;     //command input, area a
    #200;
    WE = 1'b0;
    #200;
    WE = 1'b1;          //write enable, data latched in
    #200;
  
    CLE = 1'b0;
    #200;
    ALE = 1'b1;
    IO_BUF = addr_1st;  //address cycle 1
    #200;
    WE = 1'b0;
    #200;
    WE = 1'b1;          //write enable, data latched in
    #200;
  
    IO_BUF = addr_2nd;  //address cycle 2
    #200;
    WE = 1'b0;
    #200;
    WE = 1'b1;          //write enable, data latched in
    #200;
  
    //IO_BUF = addr_3rd;  //address cycle 3
    //#200;
    //WE = 1'b0;
    //#200;
    //WE = 1'b1;          //write enable, data latched in
    //#200;

    ALE = 1'b0;
    CLE = 1'b1;
    IO_BUF = 8'hD0;     //Confirm Code
    #200;
    WE = 1'b0;
    #200;
    WE = 1'b1;          //write enable, data latched in
    #200;
  end
endtask
//#########################################################
endmodule

//=========================================================
//  TEST BENCH
//=========================================================
module test_bench;

  wire [7:0] IO   ;
  wire       CE   ;
  wire       WE   ;
  wire       RE   ;
  wire       WP   ;
  wire       CLE  ;
  wire       ALE  ;
  wire       VDD  ;
  wire       VSS  ;
  wire       RY_BY;

  NAND_DRV U_NAND_DRV
                         (
                          .IO(IO),
                          .CE(CE),
                          .WE(WE),
                          .RE(RE),
                          .WP(WP),
                          .CLE(CLE),
                          .ALE(ALE),
                          .RY_BY(RY_BY),
                          .VDD(VDD),
                          .VSS(VSS)
                         );
                        
  NAND256R3A U_NAND256R3A
                         (
                          .IO(IO),
                          .CE(CE),
                          .WE(WE),
                          .RE(RE),
                          .WP(WP),
                          .CLE(CLE),
                          .ALE(ALE),
                          .RY_BY(RY_BY),
                          .VDD(VDD),
                          .VSS(VSS)
                         );
endmodule