📄 decoder24.syr
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Release 8.2i - xst I.31Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to ./xst/projnav.tmpCPU : 0.00 / 0.80 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.80 s | Elapsed : 0.00 / 1.00 s --> Reading design: decoder24.prjTABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "decoder24.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "decoder24"Output Format : NGCTarget Device : xc2s100-6-tq144---- Source OptionsTop Module Name : decoder24Automatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Style : lutRAM Extraction : YesRAM Style : AutoROM Extraction : YesMux Style : AutoDecoder Extraction : YESPriority Encoder Extraction : YESShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESROM Style : AutoMux Extraction : YESResource Sharing : YESMultiplier Style : lutAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 100Add Generic Clock Buffer(BUFG) : 4Register Duplication : YESSlice Packing : YESPack IO Registers into IOBs : autoEquivalent register Removal : YES---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Keep Hierarchy : NORTL Output : YesGlobal Optimization : AllClockNetsWrite Timing Constraints : NOHierarchy Separator : /Bus Delimiter : <>Case Specifier : maintainSlice Utilization Ratio : 100Slice Utilization Ratio Delta : 5---- Other Optionslso : decoder24.lsoRead Cores : YEScross_clock_analysis : NOverilog2001 : YESsafe_implementation : NoOptimize Instantiated Primitives : NOtristate2logic : Yesuse_clock_enable : Yesuse_sync_set : Yesuse_sync_reset : Yes==================================================================================================================================================* HDL Compilation *=========================================================================WARNING:HDLParsers:3215 - Unit work/decoder24 is now defined in a different file: was E:/MY_DESIGN/ISE/LXJ/decoder24/decoder24.vhd, now is D:/MY_DESIGN/ISE/LXJ/decoder24/decoder24.vhdWARNING:HDLParsers:3215 - Unit work/decoder24/Behavioral is now defined in a different file: was E:/MY_DESIGN/ISE/LXJ/decoder24/decoder24.vhd, now is D:/MY_DESIGN/ISE/LXJ/decoder24/decoder24.vhdCompiling vhdl file "D:/MY_DESIGN/ISE/LXJ/decoder24/decoder24.vhd" in Library work.Architecture behavioral of Entity decoder24 is up to date.=========================================================================* Design Hierarchy Analysis *=========================================================================Analyzing hierarchy for entity <decoder24> in library <work> (architecture <behavioral>).Building hierarchy successfully finished.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <decoder24> in library <work> (Architecture <behavioral>).INFO:Xst:1561 - "D:/MY_DESIGN/ISE/LXJ/decoder24/decoder24.vhd" line 46: Mux is complete : default of case is discardedEntity <decoder24> analyzed. Unit <decoder24> generated.=========================================================================* HDL Synthesis *=========================================================================Performing bidirectional port resolution...Synthesizing Unit <decoder24>. Related source file is "D:/MY_DESIGN/ISE/LXJ/decoder24/decoder24.vhd". Found 1-of-4 decoder for signal <y>. Summary: inferred 1 Decoder(s).Unit <decoder24> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Decoders : 1 1-of-4 decoder : 1==================================================================================================================================================* Advanced HDL Synthesis *=========================================================================Loading device for application Rf_Device from file 'v100.nph' in environment C:\Xilinx.=========================================================================Advanced HDL Synthesis ReportMacro Statistics# Decoders : 1 1-of-4 decoder : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <decoder24> ...Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block decoder24, actual ratio is 0.Final Macro Processing ...=========================================================================Final Register ReportFound no macro==================================================================================================================================================* Partition Report *=========================================================================Partition Implementation Status------------------------------- No Partitions were found in this design.-------------------------------=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : decoder24.ngrTop Level Output File Name : decoder24Output Format : NGCOptimization Goal : SpeedKeep Hierarchy : NODesign Statistics# IOs : 6Cell Usage :# BELS : 4# LUT2 : 4# IO Buffers : 6# IBUF : 2# OBUF : 4=========================================================================Device utilization summary:---------------------------Selected Device : 2s100tq144-6 Number of Slices: 2 out of 1200 0% Number of 4 input LUTs: 4 out of 2400 0% Number of IOs: 6 Number of bonded IOBs: 6 out of 96 6% =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.Clock Information:------------------No clock signals found in this designAsynchronous Control Signals Information:----------------------------------------No asynchronous control signals found in this designTiming Summary:---------------Speed Grade: -6 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 8.468nsTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default path analysis Total number of paths / destination ports: 8 / 4-------------------------------------------------------------------------Delay: 8.468ns (Levels of Logic = 3) Source: a0 (PAD) Destination: y<3> (PAD) Data Path: a0 to y<3> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 4 0.776 1.440 a0_IBUF (a0_IBUF) LUT2:I1->O 1 0.549 1.035 Mdecod_y_Mshift_Result_Result<0>1 (y_0_OBUF) OBUF:I->O 4.668 y_0_OBUF (y<0>) ---------------------------------------- Total 8.468ns (5.993ns logic, 2.475ns route) (70.8% logic, 29.2% route)=========================================================================CPU : 6.53 / 7.44 s | Elapsed : 7.00 / 8.00 s --> Total memory usage is 121252 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 2 ( 0 filtered)Number of infos : 1 ( 0 filtered)⌨️ 快捷键说明
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