decoder24.vhd

来自「本程序以XILINX公司的ISE８.２为开发平台」· VHDL 代码 · 共 52 行

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:55:46 06/13/2007 
-- Design Name: 
-- Module Name:    decoder24 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoder24 is
    Port ( a1 : in  STD_LOGIC;
           a0 : in  STD_LOGIC;
           y : out  STD_LOGIC_VECTOR (3 downto 0));
end decoder24;

architecture Behavioral of decoder24 is
signal inputnum :std_logic_vector(1 downto 0);
begin
  inputnum <=a1&a0;
  process(inputnum) 
    begin
	    case inputnum is
		          when "00" =>y<="0001"; 
					 when "01" =>y<="0010"; 
					 when "10" =>y<="0100"; 
					 when "11" =>y<="1000";
                when others =>y<="1111";
       end case;
  end process;		 
end Behavioral;