clockdiv_tbw.ant

本程序以XILINX公司的ISE８.２为开发平台

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 8.2i
--  \   \         Application : ISE
--  /   /         Filename : ClockDiv_tbw.ant
-- /___/   /\     Timestamp : Wed Jun 13 10:50:34 2007
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: ClockDiv_tbw
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY ClockDiv_tbw IS
END ClockDiv_tbw;

ARCHITECTURE testbench_arch OF ClockDiv_tbw IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "D:\MY_DESIGN\ISE\LXJ\ClockDiv\ClockDiv_tbw.ano";

    COMPONENT ClockDiv
        PORT (
            reset : In std_logic;
            clk : In std_logic;
            clkdiv : Out std_logic
        );
    END COMPONENT;

    SIGNAL reset : std_logic := '0';
    SIGNAL clk : std_logic := '0';
    SIGNAL clkdiv : std_logic := 'U';

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 100 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 0 ns;

    BEGIN
        UUT : ClockDiv
        PORT MAP (
            reset => reset,
            clk => clk,
            clkdiv => clkdiv
        );

        PROCESS    -- clock process for clk
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                clk <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                clk <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS    -- Annotation process for clk
            VARIABLE TX_TIME : INTEGER := 0;

            PROCEDURE ANNOTATE_clkdiv(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", clkdiv, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, clkdiv);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
        BEGIN
            WAIT for 1 fs;
            ANNOTATE_clkdiv(0);
            WAIT for OFFSET;
            TX_TIME := TX_TIME + 0;
            ANNO_LOOP : LOOP
                --Rising Edge
                WAIT for 60 ns;
                TX_TIME := TX_TIME + 60;
                ANNOTATE_clkdiv(TX_TIME);
                WAIT for 40 ns;
                TX_TIME := TX_TIME + 40;
            END LOOP ANNO_LOOP;
        END PROCESS;

        PROCESS
            BEGIN
                -- -------------  Current Time:  240ns
                WAIT FOR 240 ns;
                reset <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  340ns
                WAIT FOR 100 ns;
                reset <= '0';
                -- -------------------------------------
                WAIT FOR 11760 ns;

                STD.TEXTIO.write(TX_OUT, string'("Total[]"));
                STD.TEXTIO.writeline(RESULTS, TX_OUT);
                ASSERT (FALSE) REPORT
                    "Success! Simulation for annotation completed"
                    SEVERITY FAILURE;
            END PROCESS;

    END testbench_arch;