clockdiv.twr

来自「本程序以XILINX公司的ISE８.２为开发平台」· TWR 代码 · 共 58 行

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Release 8.2i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

C:\Xilinx\bin\nt\trce.exe -ise D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv.ise
-intstyle ise -e 3 -l 3 -s 5 -xml ClockDiv ClockDiv.ncd -o ClockDiv.twr
ClockDiv.pcf

Design file:              clockdiv.ncd
Physical constraint file: clockdiv.pcf
Device,speed:             xc2s200,-5 (PRODUCTION 1.27 2006-05-03)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
clkdiv      |    7.666(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    6.670|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Wed Jun 13 11:00:22 2007
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 93 MB