clockdiv_tbw.tbw

来自「本程序以XILINX公司的ISE８.２为开发平台」· TBW 代码 · 共 44 行

version 3
D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv.vhd
ClockDiv
VHDL
VHDL
ClockDiv_tbw.xwv
Clocked
-
-
12000000000
ns
GSR:true
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
50000000
50000000
10000000
10000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
clkdiv
clk
reset
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
clkdiv_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
reset
clkdiv
SIGNAL_ORDER_END
-X-X-X-