clockdiv_synthesis.nlf

本程序以XILINX公司的ISE８.２为开发平台

Release 8.2i - netgen I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -insert_glbl true -w -dir netgen/synthesis
-ofmt verilog -sim ClockDiv.ngc ClockDiv_synthesis.v  

Reading design 'ClockDiv.ngc' ...
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing Verilog netlist file
'D:\MY_DESIGN\ISE\LXJ\ClockDiv\netgen\synthesis\ClockDiv_synthesis.v' ...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM
   simulation primitives and has to be used with UNISIM simulation library for
   correct compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 57868 kilobytes