clockdiv_synthesis.v

本程序以XILINX公司的ISE８.２为开发平台

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: I.31
//  \   \         Application: netgen
//  /   /         Filename: ClockDiv_synthesis.v
// /___/   /\     Timestamp: Wed Jun 13 10:54:29 2007
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim ClockDiv.ngc ClockDiv_synthesis.v 
// Device	: xc2s200-5-fg256
// Input file	: ClockDiv.ngc
// Output file	: D:\MY_DESIGN\ISE\LXJ\ClockDiv\netgen\synthesis\ClockDiv_synthesis.v
// # of Modules	: 1
// Design Name	: ClockDiv
// Xilinx        : C:\Xilinx
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23
//     Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module ClockDiv (
  clk, reset, clkdiv
);
  input clk;
  input reset;
  output clkdiv;
  wire clk_BUFGP_1;
  wire reset_IBUF_2;
  wire clkdiv_OBUF_3;
  wire _not0001;
  wire N1;
  wire N8;
  wire [3 : 0] cnt;
  wire [3 : 1] Result;
  wire [0 : 0] Mcount_cnt_lut;
  VCC XST_VCC (
    .P(N1)
  );
  FDR clkdiv_0 (
    .D(N1),
    .R(_not0001),
    .C(clk_BUFGP_1),
    .Q(clkdiv_OBUF_3)
  );
  FDC cnt_0 (
    .D(Mcount_cnt_lut[0]),
    .CLR(reset_IBUF_2),
    .C(clk_BUFGP_1),
    .Q(cnt[0])
  );
  FDC cnt_1 (
    .D(Result[1]),
    .CLR(reset_IBUF_2),
    .C(clk_BUFGP_1),
    .Q(cnt[1])
  );
  FDC cnt_2 (
    .D(Result[2]),
    .CLR(reset_IBUF_2),
    .C(clk_BUFGP_1),
    .Q(cnt[2])
  );
  FDC cnt_3 (
    .D(Result[3]),
    .CLR(reset_IBUF_2),
    .C(clk_BUFGP_1),
    .Q(cnt[3])
  );
  defparam \Mcount_cnt_xor<2>11 .INIT = 8'h6A;
  LUT3 \Mcount_cnt_xor<2>11  (
    .I0(cnt[2]),
    .I1(cnt[1]),
    .I2(cnt[0]),
    .O(Result[2])
  );
  defparam \Mcount_cnt_xor<1>11 .INIT = 16'h6466;
  LUT4 \Mcount_cnt_xor<1>11  (
    .I0(cnt[0]),
    .I1(cnt[1]),
    .I2(cnt[2]),
    .I3(cnt[3]),
    .O(Result[1])
  );
  defparam \Mcount_cnt_xor<3>11 .INIT = 16'h6CC4;
  LUT4 \Mcount_cnt_xor<3>11  (
    .I0(cnt[0]),
    .I1(cnt[3]),
    .I2(cnt[1]),
    .I3(cnt[2]),
    .O(Result[3])
  );
  defparam _not00011.INIT = 16'hFFBF;
  LUT4 _not00011 (
    .I0(cnt[1]),
    .I1(cnt[3]),
    .I2(cnt[0]),
    .I3(cnt[2]),
    .O(_not0001)
  );
  BUFGP clk_BUFGP (
    .I(clk),
    .O(clk_BUFGP_1)
  );
  IBUF reset_IBUF (
    .I(reset),
    .O(reset_IBUF_2)
  );
  OBUF clkdiv_OBUF (
    .I(clkdiv_OBUF_3),
    .O(clkdiv)
  );
  INV \Mcount_cnt_lut<0>1_INV_0  (
    .I(cnt[0]),
    .O(Mcount_cnt_lut[0])
  );
  GND XST_GND (
    .G(N8)
  );
endmodule


`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire PRLD;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule