📄 clockdiv_translate.nlf

📁 本程序以XILINX公司的ISE８.２为开发平台

💻 NLF

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Release 8.2i - netgen I.31Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.Command Line: netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm ClockDiv
-w -dir netgen/translate -ofmt vhdl -sim ClockDiv.ngd ClockDiv_translate.vhd  Reading design 'ClockDiv.ngd' ...Flattening design ...Processing design ...   Preping design's networks ...  Preping design's macros ...Writing VHDL netlist
'D:\MY_DESIGN\ISE\LXJ\ClockDiv\netgen\translate\ClockDiv_translate.vhd' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM library for correct
   compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 57868 kilobytes

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