clockdiv_map.nlf

来自「本程序以XILINX公司的ISE８.２为开发平台」· NLF 代码 · 共 30 行

NLF
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Release 8.2i - netgen I.31Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.Command Line: netgen -intstyle ise -s 5 -pcf ClockDiv.pcf -rpw 100 -tpw 0 -ar
Structure -tm ClockDiv -w -dir netgen/map -ofmt vhdl -sim ClockDiv_map.ncd
ClockDiv_map.vhd  Read and Annotate design 'ClockDiv_map.ncd' ...Loading device for application Rf_Device from file 'v200.nph' in environment
C:\Xilinx.   "ClockDiv" is an NCD, version 3.1, device xc2s200, package fg256, speed -5Loading constraints from 'ClockDiv.pcf'...The speed grade (-5) differs from the speed grade specified in the .ncd file
(-5).The number of routable networks is 8Flattening design ...Processing design ...   Preping design's networks ...  Preping design's macros ...Writing VHDL netlist 'D:\MY_DESIGN\ISE\LXJ\ClockDiv\netgen\map\ClockDiv_map.vhd'
...Writing VHDL SDF file
'D:\MY_DESIGN\ISE\LXJ\ClockDiv\netgen\map\ClockDiv_map.sdf' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM library for correct
   compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 92216 kilobytes

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