clockdiv.vhd

本程序以XILINX公司的ISE８.２为开发平台

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:46:09 06/13/2007 
-- Design Name: 
-- Module Name:    ClockDiv - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ClockDiv is
    Port ( reset : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           clkdiv : out  STD_LOGIC);
end ClockDiv;

architecture Behavioral of ClockDiv is
signal cnt : std_logic_vector(3 downto 0);
begin
process(clk,reset)
  begin
 		if reset ='1' then
			cnt<=(OTHERS =>'0');
		else 
          IF (clk'event AND clk='1' ) THEN 
				  cnt <= cnt +1; 
               IF (cnt="1001" ) THEN 
                  cnt <= (OTHERS =>'0'); 
				     END IF; 
				  END IF ; 
			 end if;
 END PROCESS;
 process(clk)
   begin
     if(clk'event and clk='1') then 
        if (cnt="1001") then 
          clkdiv <='1';
         else
          clkdiv <='0';
        end if;
     end if;
  end process;	
end Behavioral;