clockdiv_map.mrp

本程序以XILINX公司的ISE８.２为开发平台

Release 8.2i Map I.31
Xilinx Mapping Report File for Design 'ClockDiv'

Design Information
------------------
Command Line   : C:\Xilinx\bin\nt\map.exe -ise
D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv.ise -intstyle ise -p xc2s200-fg256-5 -cm
area -pr b -k 4 -c 100 -tx off -o ClockDiv_map.ncd ClockDiv.ngd ClockDiv.pcf 
Target Device  : xc2s200
Target Package : fg256
Target Speed   : -5
Mapper Version : spartan2 -- $Revision: 1.34.32.1 $
Mapped Date    : Wed Jun 13 11:00:13 2007

Design Summary
--------------
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:         4 out of  4,704    1%
  Number of 4 input LUTs:             4 out of  4,704    1%
Logic Distribution:
    Number of occupied Slices:                           2 out of  2,352    1%
    Number of Slices containing only related logic:      2 out of      2  100%
    Number of Slices containing unrelated logic:         0 out of      2    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         4 out of  4,704    1%
   Number of bonded IOBs:             2 out of    176    1%
      IOB Flip Flops:                               1
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  64
Additional JTAG gate count for IOBs:  144
Peak Memory Usage:  127 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network N8 has no load.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   1 block(s) removed
   1 block(s) optimized away
   1 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "N8" is loadless and has been removed.
 Loadless block "XST_GND" (ZERO) removed.

Optimized Block(s):
TYPE 		BLOCK
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk                                | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       |
| clkdiv                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| reset                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
No timing report for this architecture.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings