hdpdeps.ref

本程序以XILINX公司的ISE８.２为开发平台

V3 22
FL D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv.vhd 2007/06/13.10:49:41 I.31
EN work/ClockDiv -1        FL D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv.vhd \
      PB ieee/std_logic_1164 1147840849 PB ieee/std_logic_arith 1147840851 \
      PB ieee/STD_LOGIC_UNSIGNED 1147840857
AR work/ClockDiv/Behavioral -1 FL D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv.vhd \
      EN work/ClockDiv 1181702992
FL D:/MY_DESIGN/ISE/LXJ/ClockDiv/netgen/par/ClockDiv_timesim.v 2007/06/13.10:59:16 I.31
MO work/ClockDiv        FL D:/MY_DESIGN/ISE/LXJ/ClockDiv/netgen/par/ClockDiv_timesim.v \
      MI X_BUF          MI X_CKBUF        MI X_FF           MI X_INV          MI X_IPAD \
      MI X_LUT4         MI X_OBUF         MI X_ONE          MI X_OPAD         MI X_SFF \
      MI X_ZERO
FL D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv_tbw.vhw 2007/06/13.10:50:34 I.31
EN work/ClockDiv_tbw 1181703561    FL D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv_tbw.vhw \
      PB ieee/std_logic_1164 1147840849 PB ieee/std_logic_arith 1147840851 \
      PB ieee/STD_LOGIC_UNSIGNED 1147840857 PB ieee/STD_LOGIC_TEXTIO 1147840859 \
      PB std/textio 1147840824
AR work/ClockDiv_tbw/testbench_arch 1181703562 \
      FL D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv_tbw.vhw EN work/ClockDiv_tbw 1181703561 \
      CP ClockDiv       PB ieee/STD_LOGIC_TEXTIO 1147840859
FL $XILINX/verilog/src/glbl.v 2006/05/18.02:09:08 I.31
MO work/glbl            FL $XILINX/verilog/src/glbl.v