delay_vhd_synthesis.v

本程序以ISE为开发平台

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: I.31
//  \   \         Application: netgen
//  /   /         Filename: DELAY_VHD_synthesis.v
// /___/   /\     Timestamp: Tue May 08 12:54:06 2007
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim DELAY_VHD.ngc DELAY_VHD_synthesis.v 
// Device	: xc3s200-4-ft256
// Input file	: DELAY_VHD.ngc
// Output file	: D:\MY_DESIGN\ISE\LXJ\DELAY1\netgen\synthesis\DELAY_VHD_synthesis.v
// # of Modules	: 1
// Design Name	: DELAY_VHD
// Xilinx        : C:\Xilinx
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23
//     Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module DELAY_VHD (
  CLK, LATCH, TRIG, output1, OUTPUT, DATA8
);
  input CLK;
  input LATCH;
  input TRIG;
  output output1;
  output OUTPUT;
  input [7 : 0] DATA8;
  wire CLK_BUFGP_2;
  wire LATCH_BUFGP_3;
  wire TRIG_IBUF_4;
  wire output1_OBUF_5;
  wire OUTPUT_OBUF_6;
  wire cflag_7;
  wire cflag0_8;
  wire _not0010;
  wire _not0011;
  wire _not0012;
  wire _not0013;
  wire _not0014;
  wire _not0009;
  wire _not0015;
  wire _not0016;
  wire _mux0024;
  wire _mux0027;
  wire _mux0028;
  wire _mux0029;
  wire SYNC_9;
  wire _cmp_ge0000;
  wire _or0000;
  wire DATA8_7_IBUF_10;
  wire DATA8_6_IBUF_11;
  wire DATA8_5_IBUF_12;
  wire DATA8_4_IBUF_13;
  wire DATA8_3_IBUF_14;
  wire DATA8_2_IBUF_15;
  wire DATA8_1_IBUF_16;
  wire DATA8_0_IBUF_17;
  wire N0;
  wire sent1_Sclr_inv;
  wire \_mux0013<0>_mand_18 ;
  wire \_mux0013<0>_mand1 ;
  wire N4;
  wire \_mux0013<1>_mand1 ;
  wire N5;
  wire \_mux0013<2>_mand1 ;
  wire N6;
  wire \_mux0013<3>_mand1 ;
  wire N7;
  wire \_mux0013<4>_mand1 ;
  wire N8;
  wire \_mux0013<5>_mand1 ;
  wire N9;
  wire \_mux0013<6>_mand1 ;
  wire N10;
  wire \_mux0013<7>_mand1 ;
  wire N11;
  wire N112;
  wire N1;
  wire N3;
  wire N61;
  wire N91;
  wire N37;
  wire N46;
  wire N48;
  wire N50;
  wire N52;
  wire N54;
  wire N57;
  wire N611;
  wire N76;
  wire N78;
  wire N80;
  wire SYNC_1_19;
  wire N82;
  wire N83;
  wire N84;
  wire N85;
  wire N86;
  wire [2 : 0] cnt1;
  wire [1 : 0] cnt2;
  wire [7 : 0] cnt10;
  wire [1 : 0] cnt20;
  wire [3 : 2] _mux0023;
  wire [3 : 2] _mux0026;
  wire [1 : 0] sent1;
  wire [7 : 0] _mux0022;
  wire [7 : 0] DATAREG;
  wire [7 : 5] _mux0025;
  wire [1 : 0] sent1__add0000;
  wire [6 : 0] Mcompar__cmp_ge0000_cy;
  VCC XST_VCC (
    .P(N0)
  );
  defparam cnt20_0.INIT = 1'b0;
  FDE cnt20_0 (
    .D(_mux0023[3]),
    .CE(_not0011),
    .C(CLK_BUFGP_2),
    .Q(cnt20[0])
  );
  defparam cnt20_1.INIT = 1'b0;
  FDE cnt20_1 (
    .D(_mux0023[2]),
    .CE(_not0011),
    .C(CLK_BUFGP_2),
    .Q(cnt20[1])
  );
  FDE output1_0 (
    .D(_mux0024),
    .CE(_not0012),
    .C(CLK_BUFGP_2),
    .Q(output1_OBUF_5)
  );
  defparam cnt2_0.INIT = 1'b0;
  FDE cnt2_0 (
    .D(_mux0026[3]),
    .CE(_not0014),
    .C(CLK_BUFGP_2),
    .Q(cnt2[0])
  );
  defparam cnt2_1.INIT = 1'b0;
  FDE cnt2_1 (
    .D(_mux0026[2]),
    .CE(_not0014),
    .C(CLK_BUFGP_2),
    .Q(cnt2[1])
  );
  defparam cflag0.INIT = 1'b0;
  FDE cflag0 (
    .D(_mux0028),
    .CE(_not0016),
    .C(CLK_BUFGP_2),
    .Q(cflag0_8)
  );
  FDR SYNC (
    .D(N0),
    .R(_or0000),
    .C(CLK_BUFGP_2),
    .Q(SYNC_9)
  );
  defparam cflag.INIT = 1'b0;
  FDE cflag (
    .D(_mux0027),
    .CE(_not0015),
    .C(CLK_BUFGP_2),
    .Q(cflag_7)
  );
  FDE OUTPUT_1 (
    .D(_mux0029),
    .CE(N112),
    .C(CLK_BUFGP_2),
    .Q(OUTPUT_OBUF_6)
  );
  FDE cnt1_0 (
    .D(_mux0025[7]),
    .CE(_not0013),
    .C(CLK_BUFGP_2),
    .Q(cnt1[0])
  );
  FDE cnt1_1 (
    .D(_mux0025[6]),
    .CE(_not0013),
    .C(CLK_BUFGP_2),
    .Q(cnt1[1])
  );
  FDE cnt1_2 (
    .D(_mux0025[5]),
    .CE(_not0013),
    .C(CLK_BUFGP_2),
    .Q(cnt1[2])
  );
  FDE cnt10_0 (
    .D(_mux0022[7]),
    .CE(_not0010),
    .C(CLK_BUFGP_2),
    .Q(cnt10[0])
  );
  FDE cnt10_1 (
    .D(_mux0022[6]),
    .CE(_not0010),
    .C(CLK_BUFGP_2),
    .Q(cnt10[1])
  );
  FDE cnt10_2 (
    .D(_mux0022[5]),
    .CE(_not0010),
    .C(CLK_BUFGP_2),
    .Q(cnt10[2])
  );
  FDE cnt10_3 (
    .D(_mux0022[4]),
    .CE(_not0010),
    .C(CLK_BUFGP_2),
    .Q(cnt10[3])
  );
  FDE cnt10_4 (
    .D(_mux0022[3]),
    .CE(_not0010),
    .C(CLK_BUFGP_2),
    .Q(cnt10[4])
  );
  FDE cnt10_5 (
    .D(_mux0022[2]),
    .CE(_not0010),
    .C(CLK_BUFGP_2),
    .Q(cnt10[5])
  );
  FDE cnt10_6 (
    .D(_mux0022[1]),
    .CE(_not0010),
    .C(CLK_BUFGP_2),
    .Q(cnt10[6])
  );
  FDE cnt10_7 (
    .D(_mux0022[0]),
    .CE(_not0010),
    .C(CLK_BUFGP_2),
    .Q(cnt10[7])
  );
  LD DATAREG_7 (
    .D(DATA8_7_IBUF_10),
    .G(LATCH_BUFGP_3),
    .Q(DATAREG[7])
  );
  LD DATAREG_6 (
    .D(DATA8_6_IBUF_11),
    .G(LATCH_BUFGP_3),
    .Q(DATAREG[6])
  );
  LD DATAREG_5 (
    .D(DATA8_5_IBUF_12),
    .G(LATCH_BUFGP_3),
    .Q(DATAREG[5])
  );
  LD DATAREG_4 (
    .D(DATA8_4_IBUF_13),
    .G(LATCH_BUFGP_3),
    .Q(DATAREG[4])
  );
  LD DATAREG_3 (
    .D(DATA8_3_IBUF_14),
    .G(LATCH_BUFGP_3),
    .Q(DATAREG[3])
  );
  LD DATAREG_2 (
    .D(DATA8_2_IBUF_15),
    .G(LATCH_BUFGP_3),
    .Q(DATAREG[2])
  );
  LD DATAREG_1 (
    .D(DATA8_1_IBUF_16),
    .G(LATCH_BUFGP_3),
    .Q(DATAREG[1])
  );
  LD DATAREG_0 (
    .D(DATA8_0_IBUF_17),
    .G(LATCH_BUFGP_3),
    .Q(DATAREG[0])
  );
  FDRE sent1_0 (
    .D(sent1__add0000[0]),
    .R(sent1_Sclr_inv),
    .CE(_not0009),
    .C(CLK_BUFGP_2),
    .Q(sent1[0])
  );
  FDRE sent1_1 (
    .D(sent1__add0000[1]),
    .R(sent1_Sclr_inv),
    .CE(_not0009),
    .C(CLK_BUFGP_2),
    .Q(sent1[1])
  );
  MULT_AND \_mux0013<0>_mand  (
    .I0(cnt10[0]),
    .I1(\_mux0013<0>_mand_18 ),
    .LO(\_mux0013<0>_mand1 )
  );
  defparam \Mcompar__cmp_ge0000_lut<0> .INIT = 8'h87;
  LUT3 \Mcompar__cmp_ge0000_lut<0>  (
    .I0(cnt10[0]),
    .I1(\_mux0013<0>_mand_18 ),
    .I2(DATAREG[0]),
    .O(N4)
  );
  MUXCY \Mcompar__cmp_ge0000_cy<0>  (
    .CI(N0),
    .DI(\_mux0013<0>_mand1 ),
    .S(N4),
    .O(Mcompar__cmp_ge0000_cy[0])
  );
  MULT_AND \_mux0013<1>_mand  (
    .I0(cnt10[1]),
    .I1(\_mux0013<0>_mand_18 ),
    .LO(\_mux0013<1>_mand1 )
  );
  defparam \Mcompar__cmp_ge0000_lut<1> .INIT = 8'h87;
  LUT3 \Mcompar__cmp_ge0000_lut<1>  (
    .I0(cnt10[1]),
    .I1(\_mux0013<0>_mand_18 ),
    .I2(DATAREG[1]),
    .O(N5)
  );
  MUXCY \Mcompar__cmp_ge0000_cy<1>  (
    .CI(Mcompar__cmp_ge0000_cy[0]),
    .DI(\_mux0013<1>_mand1 ),
    .S(N5),
    .O(Mcompar__cmp_ge0000_cy[1])
  );
  MULT_AND \_mux0013<2>_mand  (
    .I0(cnt10[2]),
    .I1(\_mux0013<0>_mand_18 ),
    .LO(\_mux0013<2>_mand1 )
  );
  defparam \Mcompar__cmp_ge0000_lut<2> .INIT = 8'h87;
  LUT3 \Mcompar__cmp_ge0000_lut<2>  (
    .I0(cnt10[2]),
    .I1(\_mux0013<0>_mand_18 ),
    .I2(DATAREG[2]),
    .O(N6)
  );
  MUXCY \Mcompar__cmp_ge0000_cy<2>  (
    .CI(Mcompar__cmp_ge0000_cy[1]),
    .DI(\_mux0013<2>_mand1 ),
    .S(N6),
    .O(Mcompar__cmp_ge0000_cy[2])
  );
  MULT_AND \_mux0013<3>_mand  (
    .I0(cnt10[3]),
    .I1(\_mux0013<0>_mand_18 ),
    .LO(\_mux0013<3>_mand1 )
  );
  defparam \Mcompar__cmp_ge0000_lut<3> .INIT = 8'h87;
  LUT3 \Mcompar__cmp_ge0000_lut<3>  (
    .I0(cnt10[3]),
    .I1(\_mux0013<0>_mand_18 ),
    .I2(DATAREG[3]),
    .O(N7)
  );
  MUXCY \Mcompar__cmp_ge0000_cy<3>  (
    .CI(Mcompar__cmp_ge0000_cy[2]),
    .DI(\_mux0013<3>_mand1 ),
    .S(N7),
    .O(Mcompar__cmp_ge0000_cy[3])
  );
  MULT_AND \_mux0013<4>_mand  (
    .I0(cnt10[4]),
    .I1(\_mux0013<0>_mand_18 ),
    .LO(\_mux0013<4>_mand1 )
  );
  defparam \Mcompar__cmp_ge0000_lut<4> .INIT = 8'h87;
  LUT3 \Mcompar__cmp_ge0000_lut<4>  (
    .I0(cnt10[4]),
    .I1(\_mux0013<0>_mand_18 ),
    .I2(DATAREG[4]),
    .O(N8)
  );
  MUXCY \Mcompar__cmp_ge0000_cy<4>  (
    .CI(Mcompar__cmp_ge0000_cy[3]),
    .DI(\_mux0013<4>_mand1 ),
    .S(N8),
    .O(Mcompar__cmp_ge0000_cy[4])
  );
  MULT_AND \_mux0013<5>_mand  (
    .I0(cnt10[5]),
    .I1(\_mux0013<0>_mand_18 ),
    .LO(\_mux0013<5>_mand1 )
  );
  defparam \Mcompar__cmp_ge0000_lut<5> .INIT = 8'h87;
  LUT3 \Mcompar__cmp_ge0000_lut<5>  (
    .I0(cnt10[5]),
    .I1(\_mux0013<0>_mand_18 ),
    .I2(DATAREG[5]),
    .O(N9)
  );
  MUXCY \Mcompar__cmp_ge0000_cy<5>  (
    .CI(Mcompar__cmp_ge0000_cy[4]),
    .DI(\_mux0013<5>_mand1 ),
    .S(N9),
    .O(Mcompar__cmp_ge0000_cy[5])
  );
  MULT_AND \_mux0013<6>_mand  (
    .I0(cnt10[6]),
    .I1(\_mux0013<0>_mand_18 ),
    .LO(\_mux0013<6>_mand1 )
  );
  defparam \Mcompar__cmp_ge0000_lut<6> .INIT = 8'h87;
  LUT3 \Mcompar__cmp_ge0000_lut<6>  (
    .I0(cnt10[6]),
    .I1(\_mux0013<0>_mand_18 ),
    .I2(DATAREG[6]),
    .O(N10)
  );
  MUXCY \Mcompar__cmp_ge0000_cy<6>  (
    .CI(Mcompar__cmp_ge0000_cy[5]),
    .DI(\_mux0013<6>_mand1 ),
    .S(N10),
    .O(Mcompar__cmp_ge0000_cy[6])
  );
  MULT_AND \_mux0013<7>_mand  (
    .I0(cnt10[7]),
    .I1(\_mux0013<0>_mand_18 ),
    .LO(\_mux0013<7>_mand1 )
  );
  defparam \Mcompar__cmp_ge0000_lut<7> .INIT = 8'h87;
  LUT3 \Mcompar__cmp_ge0000_lut<7>  (
    .I0(cnt10[7]),
    .I1(\_mux0013<0>_mand_18 ),
    .I2(DATAREG[7]),
    .O(N11)
  );
  MUXCY \Mcompar__cmp_ge0000_cy<7>  (
    .CI(Mcompar__cmp_ge0000_cy[6]),
    .DI(\_mux0013<7>_mand1 ),
    .S(N11),
    .O(_cmp_ge0000)
  );
  defparam _mux002411.INIT = 4'hD;
  LUT2 _mux002411 (
    .I0(cnt20[1]),
    .I1(SYNC_9),
    .O(_mux0024)
  );
  defparam _mux002911.INIT = 4'hD;
  LUT2 _mux002911 (
    .I0(cnt2[1]),
    .I1(SYNC_9),
    .O(_mux0029)
  );
  defparam \sent1__add0000<1>1 .INIT = 4'h6;
  LUT2 \sent1__add0000<1>1  (
    .I0(sent1[0]),