delay_vhd.twr

本程序以ISE为开发平台

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Release 8.2i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

C:\Xilinx\bin\nt\trce.exe -ise D:/MY_DESIGN/ISE/LXJ/DELAY1/DELAY1.ise -intstyle
ise -e 3 -l 3 -s 4 -xml DELAY_VHD DELAY_VHD.ncd -o DELAY_VHD.twr DELAY_VHD.pcf

Design file:              delay_vhd.ncd
Physical constraint file: delay_vhd.pcf
Device,speed:             xc3s200,-4 (PRODUCTION 1.38 2006-05-03)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock CLK
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
TRIG        |    3.748(R)|    0.436(R)|CLK_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock LATCH
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
DATA8<0>    |    3.019(F)|   -0.464(F)|LATCH_BUFGP       |   0.000|
DATA8<1>    |    3.019(F)|   -0.463(F)|LATCH_BUFGP       |   0.000|
DATA8<2>    |    3.018(F)|   -0.463(F)|LATCH_BUFGP       |   0.000|
DATA8<3>    |    3.018(F)|   -0.463(F)|LATCH_BUFGP       |   0.000|
DATA8<4>    |    3.019(F)|   -0.463(F)|LATCH_BUFGP       |   0.000|
DATA8<5>    |    3.019(F)|   -0.463(F)|LATCH_BUFGP       |   0.000|
DATA8<6>    |    3.019(F)|   -0.463(F)|LATCH_BUFGP       |   0.000|
DATA8<7>    |    3.019(F)|   -0.464(F)|LATCH_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock CLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
OUTPUT      |    7.360(R)|CLK_BUFGP         |   0.000|
output1     |    7.359(R)|CLK_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |    7.797|         |         |         |
LATCH          |         |    8.269|         |         |
---------------+---------+---------+---------+---------+


Analysis completed Tue May 08 12:52:37 2007
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 105 MB