delay_tbw1.tbw

本程序以ISE为开发平台

version 3
D:/MY_DESIGN/ISE/LXJ/DELAY1/DELAY_VHD.vhd
DELAY_VHD
VHDL
VHDL
DELAY_tbw1.xwv
Clocked
-
-
5000000000
ns
GSR:true
PRLD:false
20000000
CLOCK_LIST_BEGIN
CLK
20000000
20000000
2000000
2000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
DATA8
CLK
LATCH
CLK
OUTPUT
CLK
TRIG
CLK
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
OUTPUT_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
CLK
LATCH
TRIG
DATA8
OUTPUT
SIGNAL_ORDER_END
-X-X-X-