delay_vhd.vhd

本程序以ISE为开发平台

----------------------------------------------------------------------------------
-- Company: ciomp
-- Engineer: liuxj
-- 
-- Create Date:    20:11:27 05/06/2007 
-- Design Name: 
-- Module Name:    DELAY_VHD - Behavioral 
-- Project Name:   DELAY
-- Target Devices: spartan3
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DELAY_VHD is
    Port ( 
	        TRIG : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           DATA8 : in  STD_LOGIC_VECTOR (7 downto 0);
           LATCH : in  STD_LOGIC;
           OUTPUT : out  STD_LOGIC;
       	  output1 : out std_logic);
end DELAY_VHD;

architecture Behavioral of DELAY_VHD is

 signal SYNC  : std_logic;
 signal sent1 : std_logic_vector(1 downto 0);
 signal DATAREG : std_logic_vector(7 downto 0);
begin 
 p1: process(clk)                   --产生SYNC信号--
	  begin
	    if CLK'event and CLK='1' then
		    if TRIG='0' then
			 sent1 <="00";
          SYNC  <='0';
          else --CLK=1 and TRIG=1
              if sent1 >="01" then --CLK=1 and TRIG=1
               SYNC <='0';
               else --CLK=1 and TRIG=1 and sent=0
              SYNC <='1';
              sent1 <=sent1+'1';
              end if;
           end if;
        end if;
    end process;		  
    
 P2: process(LATCH)
	   begin
		  if LATCH ='1' then
		  DATAREG <=DATA8;
		  end if;
	 end process;
   
 P3: process(CLK)
 
     variable cnt1  : std_logic_vector(7 downto 0); --cnt1 计算延时--
     variable cnt2  : integer range 0 to 10;  
     variable cflag : bit :='0';
     begin 
       if CLK'event and CLK ='1' then
          if SYNC ='1' then
             cflag :='1';
             cnt1 :="00000000";
             cnt2 :=0;
          end if;
          if cflag ='1' then
             if cnt1 >="0101" then
                if cnt2 >=2 then
                   cnt2 :=0;
                   cnt1 :="00000000";
                   cflag :='0';
                   OUTPUT <='0';
					 else
                   cnt2 :=cnt2+1;
                   OUTPUT <='1';
                end if;
             else
                cnt1 :=cnt1+'1';
 				end if;
			end if;
		end if;
    end process;
	 P4: process(CLK)
 
     variable cnt1  : std_logic_vector(7 downto 0);
     variable cnt2  : integer range 0 to 10;
     variable cflag : bit :='0';
     begin 
       if CLK'event and CLK ='1' then
          if SYNC ='1' then
             cflag :='1';
             cnt1 :="00000000";
             cnt2 :=0;
          end if;
          if cflag ='1' then
             if cnt1 >=DATAREG then
                if cnt2 >=2 then
                   cnt2 :=0;
                   cnt1 :="00000000";
                   cflag :='0';
                   output1 <='0';
					 else
                   cnt2 :=cnt2+1;
                   output1 <='1';
                end if;
             else
                cnt1 :=cnt1+'1';
 				end if;
			end if;
		end if;
    end process;
--P4:  process (clk)
--    begin 
--	 if clk'event and clk='1' then
--	 output1 <=OUTPUT after 80ns ;
--	 end if;
--	 end process;
 end Behavioral;