delay_tbw.vhw

本程序以ISE为开发平台

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 8.2i
--  \   \         Application : ISE
--  /   /         Filename : DELAY_tbw.vhw
-- /___/   /\     Timestamp : Tue May 08 11:52:38 2007
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: DELAY_tbw
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY DELAY_tbw IS
END DELAY_tbw;

ARCHITECTURE testbench_arch OF DELAY_tbw IS
    COMPONENT DELAY_VHD
        PORT (
            TRIG : In std_logic;
            CLK : In std_logic;
            DATA8 : In std_logic_vector (7 DownTo 0);
            LATCH : In std_logic;
            OUTPUT : Out std_logic;
            output1 : In std_logic
        );
    END COMPONENT;

    SIGNAL TRIG : std_logic := '0';
    SIGNAL CLK : std_logic := '0';
    SIGNAL DATA8 : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL LATCH : std_logic := '0';
    SIGNAL OUTPUT : std_logic := 'U';
    SIGNAL output1 : std_logic := '';

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 80 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 0 ns;

    BEGIN
        UUT : DELAY_VHD
        PORT MAP (
            TRIG => TRIG,
            CLK => CLK,
            DATA8 => DATA8,
            LATCH => LATCH,
            OUTPUT => OUTPUT,
            output1 => output1
        );

        PROCESS    -- clock process for CLK
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                CLK <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                CLK <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS
            PROCEDURE CHECK_OUTPUT(
                next_OUTPUT : std_logic;
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (OUTPUT /= next_OUTPUT) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns OUTPUT="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, OUTPUT);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_OUTPUT);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            BEGIN
                -- -------------  Current Time:  115ns
                WAIT FOR 115 ns;
                TRIG <= '1';
                LATCH <= '1';
                DATA8 <= "10100101";
                -- -------------------------------------
                -- -------------  Current Time:  195ns
                WAIT FOR 80 ns;
                TRIG <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  355ns
                WAIT FOR 160 ns;
                TRIG <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  435ns
                WAIT FOR 80 ns;
                TRIG <= '0';
                LATCH <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  595ns
                WAIT FOR 160 ns;
                TRIG <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  675ns
                WAIT FOR 80 ns;
                TRIG <= '0';
                LATCH <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  915ns
                WAIT FOR 240 ns;
                TRIG <= '1';
                LATCH <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  995ns
                WAIT FOR 80 ns;
                TRIG <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  1155ns
                WAIT FOR 160 ns;
                LATCH <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  1235ns
                WAIT FOR 80 ns;
                TRIG <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  1315ns
                WAIT FOR 80 ns;
                TRIG <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  1555ns
                WAIT FOR 240 ns;
                TRIG <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  1635ns
                WAIT FOR 80 ns;
                TRIG <= '0';
                -- -------------------------------------
                WAIT FOR 445 ns;

                IF (TX_ERROR = 0) THEN
                    STD.TEXTIO.write(TX_OUT, string'("No errors or warnings"));
                    ASSERT (FALSE) REPORT
                      "Simulation successful (not a failure).  No problems detected."
                      SEVERITY FAILURE;
                ELSE
                    STD.TEXTIO.write(TX_OUT, TX_ERROR);
                    STD.TEXTIO.write(TX_OUT,
                        string'(" errors found in simulation"));
                    ASSERT (FALSE) REPORT "Errors found during simulation"
                         SEVERITY FAILURE;
                END IF;
            END PROCESS;

    END testbench_arch;