delay_vhd.syr

本程序以ISE为开发平台

WARNING:Xst:1293 - FF/Latch  <cnt20_2> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <cnt20_3> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <cnt2_2> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <cnt2_3> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <cnt1_3> (without init value) has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <cnt1_4> (without init value) has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <cnt1_5> (without init value) has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <cnt1_6> (without init value) has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <cnt1_7> (without init value) has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1293 - FF/Latch  <cnt20_2> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <cnt20_3> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <cnt2_2> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <cnt2_3> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <cnt1_3> (without init value) has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <cnt1_4> (without init value) has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <cnt1_5> (without init value) has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <cnt1_6> (without init value) has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <cnt1_7> (without init value) has a constant value of 0 in block <DELAY_VHD>.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block DELAY_VHD, actual ratio is 1.
FlipFlop SYNC has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 23
 Flip-Flops                                            : 23

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : DELAY_VHD.ngr
Top Level Output File Name         : DELAY_VHD
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 13

Cell Usage :
# BELS                             : 77
#      GND                         : 1
#      INV                         : 3
#      LUT2                        : 9
#      LUT3                        : 17
#      LUT3_D                      : 1
#      LUT3_L                      : 1
#      LUT4                        : 22
#      LUT4_L                      : 3
#      MULT_AND                    : 8
#      MUXCY                       : 8
#      MUXF5                       : 3
#      VCC                         : 1
# FlipFlops/Latches                : 31
#      FDE                         : 19
#      FDR                         : 2
#      FDRE                        : 2
#      LD                          : 8
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 11
#      IBUF                        : 9
#      OBUF                        : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                      30  out of   1920     1%  
 Number of Slice Flip Flops:            23  out of   3840     0%  
 Number of 4 input LUTs:                56  out of   3840     1%  
 Number of IOs:                         13
 Number of bonded IOBs:                 13  out of    173     7%  
    IOB Flip Flops:                      8
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 23    |
LATCH                              | BUFGP                  | 8     |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.579ns (Maximum Frequency: 116.564MHz)
   Minimum input arrival time before clock: 4.347ns
   Maximum output required time after clock: 7.165ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 8.579ns (frequency: 116.564MHz)
  Total number of paths / destination ports: 884 / 44
-------------------------------------------------------------------------
Delay:               8.579ns (Levels of Logic = 11)
  Source:            SYNC_1 (FF)
  Destination:       cnt10_0 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: SYNC_1 to cnt10_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.720   0.801  SYNC_1 (SYNC_1)
     INV:I->O              8   0.551   1.278  _mux0013<0>_mand11_INV_0 (_mux0013<0>_mand)
     LUT3:I1->O            1   0.551   0.000  Mcompar__cmp_ge0000_lut<0> (N4)
     MUXCY:S->O            1   0.500   0.000  Mcompar__cmp_ge0000_cy<0> (Mcompar__cmp_ge0000_cy<0>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar__cmp_ge0000_cy<1> (Mcompar__cmp_ge0000_cy<1>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar__cmp_ge0000_cy<2> (Mcompar__cmp_ge0000_cy<2>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar__cmp_ge0000_cy<3> (Mcompar__cmp_ge0000_cy<3>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar__cmp_ge0000_cy<4> (Mcompar__cmp_ge0000_cy<4>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar__cmp_ge0000_cy<5> (Mcompar__cmp_ge0000_cy<5>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar__cmp_ge0000_cy<6> (Mcompar__cmp_ge0000_cy<6>)
     MUXCY:CI->O          14   0.303   1.255  Mcompar__cmp_ge0000_cy<7> (_cmp_ge0000)
     LUT4:I2->O            8   0.551   1.083  _not001011 (_not0010)
     FDE:CE                    0.602          cnt10_0
    ----------------------------------------
    Total                      8.579ns (4.162ns logic, 4.417ns route)
                                       (48.5% logic, 51.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              4.347ns (Levels of Logic = 2)
  Source:            TRIG (PAD)
  Destination:       SYNC (FF)
  Destination Clock: CLK rising

  Data Path: TRIG to SYNC
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.821   1.072  TRIG_IBUF (TRIG_IBUF)
     LUT3:I1->O            2   0.551   0.877  _or000011 (_or0000)
     FDR:R                     1.026          SYNC
    ----------------------------------------
    Total                      4.347ns (2.398ns logic, 1.949ns route)
                                       (55.2% logic, 44.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'LATCH'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              1.825ns (Levels of Logic = 1)
  Source:            DATA8<7> (PAD)
  Destination:       DATAREG_7 (LATCH)
  Destination Clock: LATCH falling

  Data Path: DATA8<7> to DATAREG_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.821   0.801  DATA8_7_IBUF (DATA8_7_IBUF)
     LD:D                      0.203          DATAREG_7
    ----------------------------------------
    Total                      1.825ns (1.024ns logic, 0.801ns route)
                                       (56.1% logic, 43.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              7.165ns (Levels of Logic = 1)
  Source:            output1 (FF)
  Destination:       output1 (PAD)
  Source Clock:      CLK rising

  Data Path: output1 to output1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   0.720   0.801  output1 (output1_OBUF)
     OBUF:I->O                 5.644          output1_OBUF (output1)
    ----------------------------------------
    Total                      7.165ns (6.364ns logic, 0.801ns route)
                                       (88.8% logic, 11.2% route)

=========================================================================
CPU : 12.55 / 14.23 s | Elapsed : 13.00 / 15.00 s
 
--> 

Total memory usage is 132480 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   32 (   0 filtered)
Number of infos    :    0 (   0 filtered)