delay_vhd.syr

本程序以ISE为开发平台

Release 8.2i - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 1.56 s | Elapsed : 0.00 / 2.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.56 s | Elapsed : 0.00 / 2.00 s
 
--> Reading design: DELAY_VHD.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "DELAY_VHD.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "DELAY_VHD"
Output Format                      : NGC
Target Device                      : xc3s200-4-ft256

---- Source Options
Top Module Name                    : DELAY_VHD
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : DELAY_VHD.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/MY_DESIGN/ISE/LXJ/DELAY1/DELAY_VHD.vhd" in Library work.
Entity <delay_vhd> compiled.
Entity <delay_vhd> (Architecture <behavioral>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <DELAY_VHD> in library <work> (architecture <behavioral>).

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <DELAY_VHD> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "D:/MY_DESIGN/ISE/LXJ/DELAY1/DELAY_VHD.vhd" line 63: The following signals are missing in the process sensitivity list:
   DATA8.
Entity <DELAY_VHD> analyzed. Unit <DELAY_VHD> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <DELAY_VHD>.
    Related source file is "D:/MY_DESIGN/ISE/LXJ/DELAY1/DELAY_VHD.vhd".
WARNING:Xst:737 - Found 8-bit latch for signal <DATAREG>.
    Found 1-bit register for signal <OUTPUT>.
    Found 1-bit register for signal <output1>.
    Found 8-bit adder for signal <$addsub0000> created at line 123.
    Found 4-bit adder for signal <$addsub0001> created at line 119.
    Found 8-bit adder for signal <$addsub0002> created at line 94.
    Found 4-bit adder for signal <$addsub0003> created at line 90.
    Found 8-bit comparator greatequal for signal <$cmp_ge0000> created at line 112.
    Found 4-bit comparator greatequal for signal <$cmp_ge0001> created at line 113.
    Found 8-bit comparator greatequal for signal <$cmp_ge0002> created at line 83.
    Found 4-bit comparator greatequal for signal <$cmp_ge0003> created at line 84.
    Found 2-bit comparator greatequal for signal <$cmp_ge0004> created at line 53.
    Found 4-bit comparator less for signal <$cmp_lt0000> created at line 113.
    Found 8-bit comparator less for signal <$cmp_lt0001> created at line 112.
    Found 4-bit comparator less for signal <$cmp_lt0002> created at line 84.
    Found 8-bit comparator less for signal <$cmp_lt0003> created at line 83.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0022>.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0025>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <cflag0>.
    Found 8-bit register for signal <cnt1>.
    Found 8-bit register for signal <cnt10>.
    Found 4-bit register for signal <cnt2>.
    Found 4-bit register for signal <cnt20>.
    Found 2-bit up counter for signal <sent1>.
    Found 1-bit register for signal <SYNC>.
    Summary:
	inferred   1 Counter(s).
	inferred  29 D-type flip-flop(s).
	inferred   4 Adder/Subtractor(s).
	inferred   9 Comparator(s).
	inferred  16 Multiplexer(s).
Unit <DELAY_VHD> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 4
 4-bit adder                                           : 2
 8-bit adder                                           : 2
# Counters                                             : 1
 2-bit up counter                                      : 1
# Registers                                            : 9
 1-bit register                                        : 5
 4-bit register                                        : 2
 8-bit register                                        : 2
# Latches                                              : 1
 8-bit latch                                           : 1
# Comparators                                          : 9
 2-bit comparator greatequal                           : 1
 4-bit comparator greatequal                           : 2
 4-bit comparator less                                 : 2
 8-bit comparator greatequal                           : 2
 8-bit comparator less                                 : 2
# Multiplexers                                         : 2
 8-bit 4-to-1 multiplexer                              : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 4
 4-bit adder                                           : 2
 8-bit adder                                           : 2
# Counters                                             : 1
 2-bit up counter                                      : 1
# Registers                                            : 29
 Flip-Flops                                            : 29
# Latches                                              : 1
 8-bit latch                                           : 1
# Comparators                                          : 9
 2-bit comparator greatequal                           : 1
 4-bit comparator greatequal                           : 2
 4-bit comparator less                                 : 2
 8-bit comparator greatequal                           : 2
 8-bit comparator less                                 : 2
# Multiplexers                                         : 2
 8-bit 4-to-1 multiplexer                              : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1988 - Unit <DELAY_VHD>: instances <Mcompar__cmp_ge0000>, <Mcompar__cmp_lt0001> of unit <LPM_COMPARE_1> and unit <LPM_COMPARE_5> are dual, second instance is removed
WARNING:Xst:1988 - Unit <DELAY_VHD>: instances <Mcompar__cmp_ge0001>, <Mcompar__cmp_lt0000> of unit <LPM_COMPARE_2> and unit <LPM_COMPARE_4> are dual, second instance is removed
WARNING:Xst:1988 - Unit <DELAY_VHD>: instances <Mcompar__cmp_ge0002>, <Mcompar__cmp_lt0003> of unit <LPM_COMPARE_3> and unit <LPM_COMPARE_6> are dual, second instance is removed
WARNING:Xst:1988 - Unit <DELAY_VHD>: instances <Mcompar__cmp_ge0003>, <Mcompar__cmp_lt0002> of unit <LPM_COMPARE_2> and unit <LPM_COMPARE_4> are dual, second instance is removed

Optimizing unit <DELAY_VHD> ...
WARNING:Xst:1293 - FF/Latch  <cnt20_2> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <cnt20_3> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <cnt2_2> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <cnt2_3> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1293 - FF/Latch  <cnt20_2> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <cnt20_3> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <cnt2_2> has a constant value of 0 in block <DELAY_VHD>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <cnt2_3> has a constant value of 0 in block <DELAY_VHD>.