ccdout.chk

来自「CCD信号由于其特殊性,一般不能有信号源产生,本程序采用VHDL语言」· CHK 代码 · 共 40 行

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|  P a r t i t i o n    S u c c e e d  |
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0 Group(s)

GCLK0: 0=clock.p
----------------- B l o c k 0 ------------------
PLApt(13/56), Fanin(5/38), Clk(1/3), Bct(1/4), Pin(5/16), Mcell(8/16)
PLApts[13/53] 3 4 5 8 2 6 14 7 10 12 () () () () () () () () () 13 () () () () () () () () () () () () () () 
              () () () () () () () () () () () () () () () 9 () () 11
Fanins[ 5] cnt<0>.n cnt<1>.n cnt<2>.n cnt<3>.n En.p
clk[1] clock 
CTC: (pt=2) cnt<2> cnt<3> ;
CTR: 
CTS: 
CTE: 
vref: [0]
Signal[ 9] [Date_out<0>(49),Date_out<0>(33)] [Date_out<1>(46),Date_out<1>(37)]  
           [Date_out<2>(48),Date_out<2>(34)] [Date_out<3>(47),Date_out<3>(36)] [cnt<0>,En(38)] [cnt<2>(60)]  
           [cnt<3>(59)] [cnt<1>(58)] 
Signal[ 9] [ 0: cnt<0>(45) En(38)  ][ 1: Date_out<1>(46) Date_out<1>(37)  ][ 2: Date_out<3>(47)  
           Date_out<3>(36)  ][ 3: Date_out<2>(48) Date_out<2>(34)  ][ 4: Date_out<0>(49) Date_out<0>(33)  ] 
           [ 5: (32)  ][ 6: (31)  ][ 7: (30)  ][ 8: (29)  ][ 9: (28)  ][ 10: (27)  ][ 11: (23)  ][ 12: (22)  
            ][ 13: cnt<1>(58) (21)  ][ 14: cnt<3>(59) (20)  ][ 15: cnt<2>(60) (19)  ]
----------------- B l o c k 1 ------------------
PLApt(0/56), Fanin(0/38), Clk(0/3), Bct(0/4), Pin(1/16), Mcell(0/16)
PLApts[0/0]
Fanins[ 0]
clk[0] 
CTC: 
CTR: 
CTS: 
CTE: 
vref: [0]
Signal[ 1] [clock(43)] 
Signal[ 1] [ 0: (39)  ][ 1: (40)  ][ 2: (41)  ][ 3: (42)  ][ 4: clock(43)  ][ 5: (44)  ][ 6: (1)  ][ 7: (2)  
            ][ 8: (3)  ][ 9: (5)  ][ 10: (6)  ][ 11: (8)  ][ 12: (12)  ][ 13: (13)  ][ 14: (14)  ][ 15: (16)  
            ]