📄 ccdout.rpt
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cpldfit: version I.31 Xilinx Inc.
Fitter Report
Design Name: CCDOUT Date: 6-11-2007, 9:02PM
Device Used: XA2C32A-6-VQ44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
8 /32 ( 25%) 13 /112 ( 12%) 5 /80 ( 6%) 8 /32 ( 25%) 6 /33 ( 18%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO CTC CTR CTS CTE
Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1 8/16 5/40 13/56 4/16 1/1* 0/1 0/1 0/1
FB2 0/16 0/40 0/56 0/16 0/1 0/1 0/1 0/1
----- ------- ------- ----- --- --- --- ---
Total 8/32 5/80 13/112 4/32 1/2 0/2 0/2 0/2
CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable
* - Resource is exhausted
** Global Control Resources **
GCK GSR GTS
Used/Tot Used/Tot Used/Tot
1/3 0/1 0/4
Signal 'clock' mapped onto global clock net GCK0.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
| I : 0 1
Input : 1 1 | I/O : 3 24
Output : 4 4 | GCK/IO : 1 3
Bidirectional : 0 0 | GTS/IO : 2 4
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 6 6
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 4 Outputs **
Signal Total Total Loc Pin Pin Pin I/O I/O Slew Reg Reg Init
Name Pts Inps No. Type Use STD Style Rate Use State
Date_out<1> 4 4 FB1_2 37 I/O O LVCMOS18 FAST LATCH RESET
Date_out<3> 5 4 FB1_3 36 I/O O LVCMOS18 FAST LATCH RESET
Date_out<2> 2 4 FB1_4 34 GTS/I/O O LVCMOS18 FAST LATCH RESET
Date_out<0> 5 4 FB1_5 33 GTS/I/O O LVCMOS18 FAST LATCH RESET
** 4 Buried Nodes **
Signal Total Total Loc Reg Reg Init
Name Pts Inps Use State
cnt<0> 0 0 FB1_1 TFF RESET
cnt<1> 1 2 FB1_14 TFF RESET
cnt<3> 1 4 FB1_15 TFF/S SET
cnt<2> 2 5 FB1_16 TFF/S SET
** 2 Inputs **
Signal Loc Pin Pin Pin I/O I/O
Name No. Type Use STD Style
En FB1_1 38 I/O I LVCMOS18 KPR
clock FB2_5 43 GCK/I/O GCK LVCMOS18 KPR
Legend:
Pin No. - ~ - User Assigned
I/O Style - OD - OpenDrain
- PU - Pullup
- KPR - Keeper
- S - SchmittTrigger
- DG - DataGate
Reg Use - LATCH - Transparent latch
- DFF - D-flip-flop
- DEFF - D-flip-flop with clock enable
- TFF - T-flip-flop
- TDFF - Dual-edge-triggered T-flip-flop
- DDFF - Dual-edge-triggered flip-flop
- DDEFF - Dual-edge-triggered flip-flop with clock enable
/S (after any above flop/latch type) indicates initial state is Set
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
VRF - Vref
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 5/35
Number of function block control terms used/remaining: 1/3
Number of PLA product terms used/remaining: 13/43
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
cnt<0> 0 FB1_1 38 I/O I
Date_out<1> 4 FB1_2 37 I/O O +
Date_out<3> 5 FB1_3 36 I/O O +
Date_out<2> 2 FB1_4 34 GTS/I/O O +
Date_out<0> 5 FB1_5 33 GTS/I/O O +
(unused) 0 FB1_6 32 GTS/I/O
(unused) 0 FB1_7 31 GTS/I/O
(unused) 0 FB1_8 30 GSR/I/O
(unused) 0 FB1_9 29 I/O
(unused) 0 FB1_10 28 I/O
(unused) 0 FB1_11 27 I/O
(unused) 0 FB1_12 23 I/O
(unused) 0 FB1_13 22 I/O
cnt<1> 1 FB1_14 21 I/O (b)
cnt<3> 1 FB1_15 20 I/O (b)
cnt<2> 2 FB1_16 19 I/O (b)
Signals Used by Logic in Function Block
1: En 3: cnt<1> 5: cnt<3>
2: cnt<0> 4: cnt<2>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Date_out<1> .XXXX................................... 4
Date_out<3> .XXXX................................... 4
Date_out<2> .XXXX................................... 4
Date_out<0> .XXXX................................... 4
cnt<1> XX...................................... 2
cnt<3> XXXX.................................... 4
cnt<2> XXXXX................................... 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB2_1 39 I/O
(unused) 0 FB2_2 40 I/O
(unused) 0 FB2_3 41 I/O
(unused) 0 FB2_4 42 I/O
(unused) 0 FB2_5 43 GCK/I/O GCK
(unused) 0 FB2_6 44 GCK/I/O
(unused) 0 FB2_7 1 GCK/I/O
(unused) 0 FB2_8 2 I/O
(unused) 0 FB2_9 3 I/O
(unused) 0 FB2_10 5 I/O
(unused) 0 FB2_11 6 I/O
(unused) 0 FB2_12 8 I/O
(unused) 0 FB2_13 12 I/O
(unused) 0 FB2_14 13 I/O
(unused) 0 FB2_15 14 I/O
(unused) 0 FB2_16 16 I/O
******************************* Equations ********************************
********** Mapped Logic **********
LDCP_Date_out0: LDCP port map (Date_out(0),Date_out_D(0),NOT ,'0','0');
Date_out_D(0) <= ((NOT cnt(2) AND cnt(1) AND cnt(0))
OR (NOT cnt(2) AND cnt(1) AND NOT cnt(3))
OR (NOT cnt(2) AND NOT cnt(1) AND cnt(3))
OR (cnt(2) AND NOT cnt(1) AND cnt(0) AND NOT cnt(3)));
LDCP_Date_out1: LDCP port map (Date_out(1),Date_out_D(1),NOT ,'0','0');
Date_out_D(1) <= NOT (((cnt(2) AND cnt(3))
OR (NOT cnt(2) AND NOT cnt(1) AND cnt(0) AND cnt(3))
OR (NOT cnt(2) AND NOT cnt(1) AND NOT cnt(0) AND NOT cnt(3))));
LDCP_Date_out2: LDCP port map (Date_out(2),Date_out_D(2),NOT ,'0','0');
Date_out_D(2) <= (cnt(2) AND cnt(1) AND NOT cnt(0) AND NOT cnt(3));
LDCP_Date_out3: LDCP port map (Date_out(3),Date_out_D(3),NOT ,'0','0');
Date_out_D(3) <= NOT (((cnt(2) AND cnt(3))
OR (cnt(2) AND cnt(1) AND NOT cnt(0) AND NOT cnt(3))
OR (NOT cnt(2) AND cnt(1) AND cnt(0) AND NOT cnt(3))
OR (NOT cnt(2) AND NOT cnt(1) AND NOT cnt(0) AND NOT cnt(3))));
FDCPE_cnt0: FDCPE port map (cnt(0),En,clock,'0','0','1');
FTCPE_cnt1: FTCPE port map (cnt(1),cnt_T(1),clock,'0','0','1');
cnt_T(1) <= (En AND NOT cnt(0));
FTCPE_cnt2: FTCPE port map (cnt(2),cnt_T(2),clock,'0','0','1');
cnt_T(2) <= ((cnt(2) AND En AND NOT cnt(1) AND NOT cnt(0))
OR (En AND NOT cnt(1) AND NOT cnt(0) AND cnt(3)));
FTCPE_cnt3: FTCPE port map (cnt(3),cnt_T(3),clock,'0','0','1');
cnt_T(3) <= (NOT cnt(2) AND En AND NOT cnt(1) AND NOT cnt(0));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FDDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
FTDCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XA2C32A-6-VQ44
--------------------------------
/44 43 42 41 40 39 38 37 36 35 34 \
| 1 33 |
| 2 32 |
| 3 31 |
| 4 30 |
| 5 XA2C32A-6-VQ44 29 |
| 6 28 |
| 7 27 |
| 8 26 |
| 9 25 |
| 10 24 |
| 11 23 |
\ 12 13 14 15 16 17 18 19 20 21 22 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 KPR 23 KPR
2 KPR 24 TDO
3 KPR 25 GND
4 GND 26 VCCIO-1.8
5 KPR 27 KPR
6 KPR 28 KPR
7 VCCIO-1.8 29 KPR
8 KPR 30 KPR
9 TDI 31 KPR
10 TMS 32 KPR
11 TCK 33 Date_out<0>
12 KPR 34 Date_out<2>
13 KPR 35 VCCAUX
14 KPR 36 Date_out<3>
15 VCC 37 Date_out<1>
16 KPR 38 En
17 GND 39 KPR
18 KPR 40 KPR
19 KPR 41 KPR
20 KPR 42 KPR
21 KPR 43 clock
22 KPR 44 KPR
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
KPR = Unused I/O with weak keeper (leave unconnected)
WPU = Unused I/O with weak pull up (leave unconnected)
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
VCCAUX = Power supply for JTAG pins
VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I
VCCIO-1.8 = I/O supply voltage for LVCMOS18
VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I
VREF = Reference voltage for indicated input standard
*VREF = Reference voltage pin selected by software
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xa2c*-*-*
Optimization Method : DENSITY
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Set Unused I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Enable Input Registers : ON
Function Block Fan-in Limit : 38
Use DATA_GATE Attribute : ON
Set Tristate Outputs to Termination Mode : KEEPER
Default Voltage Standard for All Outputs : LVCMOS18
Input Limit : 32
Pterm Limit : 28
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