isim.log

CCD信号由于其特殊性,一般不能有信号源产生,本程序采用VHDL语言

 command line:
   ./CCDOUT_tbw_isim_beh.exe
     -intstyle  ise
     -ipchost  localhost
     -ipcport  3996

Thu May 17 17:14:13 2007

Total Line Count = 808

 Elaboration time 0.015625 sec.

 Estimate current memory usage 47.1941 Meg. 

 Total signals 7
 Total nets 10
 Total signal drivers 4
 Total blocks 7
 Total primitive blocks 1
 Total processes 3
ntrace select -o on -n /CCDOUT_tbw/en 
ntrace select -o on -n /CCDOUT_tbw/clock 
ntrace select -o on -n /CCDOUT_tbw/date_out 
ntrace select -o on -n /CCDOUT_tbw/date_out 
ntrace select -o on -n /CCDOUT_tbw/date_out 
ntrace select -o on -n /CCDOUT_tbw/date_out 
ntrace select -o on -n /CCDOUT_tbw/date_out 
ntrace start 
run all 
Simulator is doing circuit initialization process.
Finished circuit initialization process.