ccdout_tbw.tbw

CCD信号由于其特殊性,一般不能有信号源产生,本程序采用VHDL语言

version 3
D:/MY_DESIGN/ISE/LXJ/CCDOUT/CCDOUT.vhd
CCDOUT
VHDL
VHDL
CCDOUT_tbw.xwv
Clocked
-
-
3000000000
ns
GSR:true
PRLD:false
100000000
CLOCK_LIST_BEGIN
clock
50000000
50000000
5000000
5000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
Date_out
clock
En
clock
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
Date_out_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clock
En
Date_out
SIGNAL_ORDER_END
-X-X-X-