ccdout.vhd

CCD信号由于其特殊性,一般不能有信号源产生,本程序采用VHDL语言

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:39:20 04/28/2007 
-- Design Name: 
-- Module Name:    CCDOUT - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CCDOUT is
    Port ( En : in  STD_LOGIC;
           clock : in  STD_LOGIC;
           Date_out : out  STD_LOGIC_VECTOR (3 downto 0));
end CCDOUT;

architecture Behavioral of CCDOUT is
signal cnt : STD_LOGIC_VECTOR (3 downto 0) :="1100";
  begin
    process (clock,En)
  begin
  if En='1' then
    if clock='1' and clock'event then
		if cnt ="0000" then
			cnt <= "1011";
		else 
			cnt <= cnt - 1;
		end if;
	 end if;
	 end if;
		
			if cnt ="1011" then
				Date_out <="1011";
			elsif cnt ="1010" then
LOOP1:	for i IN 3 downto 0 loop
				Date_out <="1010";
			 end loop; 
				
			elsif cnt ="1001" then
				Date_out <="1001";
			elsif cnt ="1000" then
				Date_out <= "1011";
			elsif cnt ="0111" then
				Date_out <="1010";
			elsif cnt ="0110" then
            Date_out <="0110";
         elsif cnt ="0101" then
            Date_out <="1011";
         elsif cnt ="0100" then
            Date_out <="1010";
         elsif cnt ="0011" then
            Date_out <="0011";
			elsif cnt ="0010" then
            Date_out <="1011";
         elsif cnt ="0001" then
            Date_out <="1010";
         elsif cnt ="0000" then
             Date_out <="0000";			
			end if;
       			
		end  process;
end Behavioral;