ascii.htm

CCD信号由于其特殊性,一般不能有信号源产生,本程序采用VHDL语言

(unused)                      0     FB2_5   43   GCK/I/O GCK   
(unused)                      0     FB2_6   44   GCK/I/O       
(unused)                      0     FB2_7   1    GCK/I/O       
(unused)                      0     FB2_8   2    I/O           
(unused)                      0     FB2_9   3    I/O           
(unused)                      0     FB2_10  5    I/O           
(unused)                      0     FB2_11  6    I/O           
(unused)                      0     FB2_12  8    I/O           
(unused)                      0     FB2_13  12   I/O           
(unused)                      0     FB2_14  13   I/O           
(unused)                      0     FB2_15  14   I/O           
(unused)                      0     FB2_16  16   I/O           
*******************************  Equations  ********************************

********** Mapped Logic **********

LDCP_Date_out0: LDCP port map (Date_out(0),Date_out_D(0),NOT ,'0','0');
Date_out_D(0) <= ((NOT cnt(2) AND cnt(1) AND cnt(0))
	OR (NOT cnt(2) AND cnt(1) AND NOT cnt(3))
	OR (NOT cnt(2) AND NOT cnt(1) AND cnt(3))
	OR (cnt(2) AND NOT cnt(1) AND cnt(0) AND NOT cnt(3)));

LDCP_Date_out1: LDCP port map (Date_out(1),Date_out_D(1),NOT ,'0','0');
Date_out_D(1) <= NOT (((cnt(2) AND cnt(3))
	OR (NOT cnt(2) AND NOT cnt(1) AND cnt(0) AND cnt(3))
	OR (NOT cnt(2) AND NOT cnt(1) AND NOT cnt(0) AND NOT cnt(3))));

LDCP_Date_out2: LDCP port map (Date_out(2),Date_out_D(2),NOT ,'0','0');
Date_out_D(2) <= (cnt(2) AND cnt(1) AND NOT cnt(0) AND NOT cnt(3));

LDCP_Date_out3: LDCP port map (Date_out(3),Date_out_D(3),NOT ,'0','0');
Date_out_D(3) <= NOT (((cnt(2) AND cnt(3))
	OR (cnt(2) AND cnt(1) AND NOT cnt(0) AND NOT cnt(3))
	OR (NOT cnt(2) AND cnt(1) AND cnt(0) AND NOT cnt(3))
	OR (NOT cnt(2) AND NOT cnt(1) AND NOT cnt(0) AND NOT cnt(3))));

FDCPE_cnt0: FDCPE port map (cnt(0),En,clock,'0','0','1');

FTCPE_cnt1: FTCPE port map (cnt(1),cnt_T(1),clock,'0','0','1');
cnt_T(1) <= (En AND NOT cnt(0));

FTCPE_cnt2: FTCPE port map (cnt(2),cnt_T(2),clock,'0','0','1');
cnt_T(2) <= ((cnt(2) AND En AND NOT cnt(1) AND NOT cnt(0))
	OR (En AND NOT cnt(1) AND NOT cnt(0) AND cnt(3)));

FTCPE_cnt3: FTCPE port map (cnt(3),cnt_T(3),clock,'0','0','1');
cnt_T(3) <= (NOT cnt(2) AND En AND NOT cnt(1) AND NOT cnt(0));


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FDDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 FTDCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XA2C32A-6-VQ44


   --------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 \
 | 1                             33 | 
 | 2                             32 | 
 | 3                             31 | 
 | 4                             30 | 
 | 5         XA2C32A-6-VQ44      29 | 
 | 6                             28 | 
 | 7                             27 | 
 | 8                             26 | 
 | 9                             25 | 
 | 10                            24 | 
 | 11                            23 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 KPR                              23 KPR                           
  2 KPR                              24 TDO                           
  3 KPR                              25 GND                           
  4 GND                              26 VCCIO-1.8                     
  5 KPR                              27 KPR                           
  6 KPR                              28 KPR                           
  7 VCCIO-1.8                        29 KPR                           
  8 KPR                              30 KPR                           
  9 TDI                              31 KPR                           
 10 TMS                              32 KPR                           
 11 TCK                              33 Date_out<0>                   
 12 KPR                              34 Date_out<2>                   
 13 KPR                              35 VCCAUX                        
 14 KPR                              36 Date_out<3>                   
 15 VCC                              37 Date_out<1>                   
 16 KPR                              38 En                            
 17 GND                              39 KPR                           
 18 KPR                              40 KPR                           
 19 KPR                              41 KPR                           
 20 KPR                              42 KPR                           
 21 KPR                              43 clock                         
 22 KPR                              44 KPR                           


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xa2c*-*-*
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : KEEPER
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28
</pre>
<form><span class="pgRef"><table width="90%" align="center"><tr>
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
</tr></table></span></form>
</body></html>