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cpldfit: version I.31 Xilinx Inc.
Fitter Report
Design Name: CCDOUT Date: 6-11-2007, 9:02PM
Device Used: XA2C32A-6-VQ44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
8 /32 ( 25%) 13 /112 ( 12%) 5 /80 ( 6%) 8 /32 ( 25%) 6 /33 ( 18%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO CTC CTR CTS CTE
Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1 8/16 5/40 13/56 4/16 1/1* 0/1 0/1 0/1
FB2 0/16 0/40 0/56 0/16 0/1 0/1 0/1 0/1
----- ------- ------- ----- --- --- --- ---
Total 8/32 5/80 13/112 4/32 1/2 0/2 0/2 0/2
CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable
* - Resource is exhausted
** Global Control Resources **
GCK GSR GTS
Used/Tot Used/Tot Used/Tot
1/3 0/1 0/4
Signal 'clock' mapped onto global clock net GCK0.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
| I : 0 1
Input : 1 1 | I/O : 3 24
Output : 4 4 | GCK/IO : 1 3
Bidirectional : 0 0 | GTS/IO : 2 4
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 6 6
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 4 Outputs **
Signal Total Total Loc Pin Pin Pin I/O I/O Slew Reg Reg Init
Name Pts Inps No. Type Use STD Style Rate Use State
Date_out<1> 4 4 FB1_2 37 I/O O LVCMOS18 FAST LATCH RESET
Date_out<3> 5 4 FB1_3 36 I/O O LVCMOS18 FAST LATCH RESET
Date_out<2> 2 4 FB1_4 34 GTS/I/O O LVCMOS18 FAST LATCH RESET
Date_out<0> 5 4 FB1_5 33 GTS/I/O O LVCMOS18 FAST LATCH RESET
** 4 Buried Nodes **
Signal Total Total Loc Reg Reg Init
Name Pts Inps Use State
cnt<0> 0 0 FB1_1 TFF RESET
cnt<1> 1 2 FB1_14 TFF RESET
cnt<3> 1 4 FB1_15 TFF/S SET
cnt<2> 2 5 FB1_16 TFF/S SET
** 2 Inputs **
Signal Loc Pin Pin Pin I/O I/O
Name No. Type Use STD Style
En FB1_1 38 I/O I LVCMOS18 KPR
clock FB2_5 43 GCK/I/O GCK LVCMOS18 KPR
Legend:
Pin No. - ~ - User Assigned
I/O Style - OD - OpenDrain
- PU - Pullup
- KPR - Keeper
- S - SchmittTrigger
- DG - DataGate
Reg Use - LATCH - Transparent latch
- DFF - D-flip-flop
- DEFF - D-flip-flop with clock enable
- TFF - T-flip-flop
- TDFF - Dual-edge-triggered T-flip-flop
- DDFF - Dual-edge-triggered flip-flop
- DDEFF - Dual-edge-triggered flip-flop with clock enable
/S (after any above flop/latch type) indicates initial state is Set
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
VRF - Vref
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 5/35
Number of function block control terms used/remaining: 1/3
Number of PLA product terms used/remaining: 13/43
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
cnt<0> 0 FB1_1 38 I/O I
Date_out<1> 4 FB1_2 37 I/O O +
Date_out<3> 5 FB1_3 36 I/O O +
Date_out<2> 2 FB1_4 34 GTS/I/O O +
Date_out<0> 5 FB1_5 33 GTS/I/O O +
(unused) 0 FB1_6 32 GTS/I/O
(unused) 0 FB1_7 31 GTS/I/O
(unused) 0 FB1_8 30 GSR/I/O
(unused) 0 FB1_9 29 I/O
(unused) 0 FB1_10 28 I/O
(unused) 0 FB1_11 27 I/O
(unused) 0 FB1_12 23 I/O
(unused) 0 FB1_13 22 I/O
cnt<1> 1 FB1_14 21 I/O (b)
cnt<3> 1 FB1_15 20 I/O (b)
cnt<2> 2 FB1_16 19 I/O (b)
Signals Used by Logic in Function Block
1: En 3: cnt<1> 5: cnt<3>
2: cnt<0> 4: cnt<2>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Date_out<1> .XXXX................................... 4
Date_out<3> .XXXX................................... 4
Date_out<2> .XXXX................................... 4
Date_out<0> .XXXX................................... 4
cnt<1> XX...................................... 2
cnt<3> XXXX.................................... 4
cnt<2> XXXXX................................... 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB2_1 39 I/O
(unused) 0 FB2_2 40 I/O
(unused) 0 FB2_3 41 I/O
(unused) 0 FB2_4 42 I/O
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