📄 ccdout.cxt
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<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE Document [
<!ELEMENT Document (Net*, Globals*, Lb+)><!ATTLIST Document Version CDATA #REQUIRED Module CDATA #REQUIRED Date CDATA #REQUIRED Device CDATA #REQUIRED><!ELEMENT Globals (InBuf*, GlblBuf*, ClkDiv*, SDot*)><!ELEMENT Net (Activity?)><!ATTLIST Net NNm CDATA #REQUIRED IoT (in | out | bidi | none) #REQUIRED Loc CDATA #IMPLIED ClkT (G | U) #IMPLIED SNm CDATA #IMPLIED><!ELEMENT Activity EMPTY><!ATTLIST Activity Freq CDATA #IMPLIED DutyCycle CDATA #IMPLIED><!ELEMENT InBuf (IPort, OPort*)><!ATTLIST InBuf Nm CDATA #REQUIRED IOS (LVTTL | LVCMOS15 | LVCMOS18 | LVCMOS25 | LVCMOS33 | HSTL_I | SSTL2_I | SSTL3_I | STRIG) #REQUIRED DataGate (Y | N) #REQUIRED><!ELEMENT GlblBuf (IPort)><!ATTLIST GlblBuf Nm CDATA #REQUIRED GType (GOE | GSR | GCK | GCK2 | CDRST | GDGATE) #REQUIRED><!ELEMENT ClkDiv (IPort, OPort)><!ATTLIST ClkDiv Nm CDATA #REQUIRED DivideBy (2 | 4 | 6 | 8 | 10 | 12 | 14 | 16) #REQUIRED><!ELEMENT SDot (IPort, OPort)><!ATTLIST SDot Nm CDATA #REQUIRED><!ELEMENT Lb (LbT*, Mc*, SDot*)><!ATTLIST Lb Nm CDATA #REQUIRED><!ELEMENT LbT (OPort, IPort+)><!ATTLIST LbT Nm CDATA #REQUIRED PtT (XBR_A | XBR_B | XBR_C | XBR_CT | XBR_CT_X) #REQUIRED><!ELEMENT Mc (RMux*, ClkMux?, XorMux?, OeMux?, FbMux*, InBuf?, OutBuf?, DFlop?, Or?, SDot*)><!ATTLIST Mc Nm CDATA #REQUIRED><!ELEMENT Or (OPort, IPort+)><!ATTLIST Or Nm CDATA #REQUIRED><!ELEMENT ClkMux (IPort, OPort)><!ATTLIST ClkMux Nm CDATA #REQUIRED Rate (1 | 2) #IMPLIED><!ELEMENT RMux (IPort)><!ATTLIST RMux Nm CDATA #REQUIRED><!ELEMENT OeMux (IPort)><!ATTLIST OeMux Nm CDATA #REQUIRED><!ELEMENT XorMux (IPort)><!ATTLIST XorMux Nm CDATA #REQUIRED><!ELEMENT FbMux (IPort)><!ATTLIST FbMux Nm CDATA #REQUIRED><!ELEMENT OutBuf (IPort, OPort, CntlPort*)><!ATTLIST OutBuf Nm CDATA #REQUIRED IOS (LVTTL | LVCMOS15 | LVCMOS18 | LVCMOS25 | LVCMOS33 | HSTL_I | SSTL2_I | SSTL3_I | STRIG) #REQUIRED><!ELEMENT DFlop (FlopPort+)><!ATTLIST DFlop Nm CDATA #REQUIRED><!ELEMENT FlopPort EMPTY><!ATTLIST FlopPort NNm CDATA #REQUIRED Port (D | CLK | Q | RST | PST | CE) #REQUIRED><!ELEMENT IPort EMPTY><!ATTLIST IPort NNm CDATA #REQUIRED><!ELEMENT OPort EMPTY><!ATTLIST OPort NNm CDATA #REQUIRED><!ELEMENT CntlPort EMPTY><!ATTLIST CntlPort NNm CDATA #REQUIRED>]>
<Document Date="Jun 11 21:03:00 2007" Device="XA2C32A-6VQ44" Module="CCDOUT" Version="2"><Net IoT="in" Loc="FB2_5" NNm="clock" SNm="clock" ClkT="G"/><Net IoT="none" NNm="FB1_PT52" SNm="cnt<3>_MC.D"/><Net IoT="none" NNm="FB1_PT19" SNm="Date_out<2>_MC.D"/><Net IoT="none" NNm="FB1_PT49" SNm="cnt<1>_MC.D"/><Net IoT="none" NNm="FB1_2_OR" SNm="Date_out<1>_MC.D"/><Net IoT="none" NNm="FB1_3_OR" SNm="Date_out<3>_MC.D"/><Net IoT="none" NNm="FB1_5_OR" SNm="Date_out<0>_MC.D"/><Net IoT="none" NNm="FB2_5_I" SNm="clock_II/FCLK"/><Net IoT="none" NNm="FB1_5_Q" SNm="Date_out<0>_MC.Q"/><Net IoT="none" NNm="FB1_2_Q" SNm="Date_out<1>_MC.Q"/><Net IoT="none" NNm="FB1_4_Q" SNm="Date_out<2>_MC.Q"/><Net IoT="none" NNm="FB1_3_Q" SNm="Date_out<3>_MC.Q"/><Net IoT="none" NNm="FB1_1_MC_CLK" SNm="FB1_1_MC_CLK"/><Net IoT="none" NNm="FB1_2_MC_CLK" SNm="FB1_2_MC_CLK"/><Net IoT="none" NNm="FB1_3_MC_CLK" SNm="FB1_3_MC_CLK"/><Net IoT="none" NNm="FB1_4_MC_CLK" SNm="FB1_4_MC_CLK"/><Net IoT="none" NNm="FB1_5_MC_CLK" SNm="FB1_5_MC_CLK"/><Net IoT="none" NNm="FB1_16_OR" SNm="cnt<2>_MC.D"/><Net IoT="none" NNm="FB1_14_MC_CLK" SNm="FB1_14_MC_CLK"/><Net IoT="none" NNm="FB1_15_MC_CLK" SNm="FB1_15_MC_CLK"/><Net IoT="none" NNm="FB1_16_MC_CLK" SNm="FB1_16_MC_CLK"/><Net IoT="in" Loc="FB1_1" NNm="En" SNm="En"/><Net IoT="none" NNm="FB1_1_I" SNm="cnt<0>_MC.D"/><Net IoT="none" NNm="PT_GND" SNm="PT_GND"/><Net IoT="out" Loc="FB1_5" NNm="Date_out<0>" SNm="Date_out<0>"/><Net IoT="out" Loc="FB1_2" NNm="Date_out<1>" SNm="Date_out<1>"/><Net IoT="out" Loc="FB1_4" NNm="Date_out<2>" SNm="Date_out<2>"/><Net IoT="out" Loc="FB1_3" NNm="Date_out<3>" SNm="Date_out<3>"/><Net IoT="none" NNm="FB1_PT0" SNm="FB1_PT0"/><Net IoT="none" NNm="FB1_PT1" SNm="FB1_PT1"/><Net IoT="none" NNm="FB1_PT2" SNm="FB1_PT2"/><Net IoT="none" NNm="FB1_1_Q" SNm="cnt<0>_MC.Q"/><Net IoT="none" NNm="FB1_PT3" SNm="FB1_PT3"/><Net IoT="none" NNm="FB1_14_Q" SNm="cnt<1>_MC.Q"/><Net IoT="none" NNm="FB1_PT4" SNm="FOOBAR1__ctinst/4"/><Net IoT="none" NNm="FB1_16_Q" SNm="cnt<2>_MC.Q"/><Net IoT="none" NNm="FB1_PT5" SNm="FB1_PT5"/><Net IoT="none" NNm="FB1_15_Q" SNm="cnt<3>_MC.Q"/><Net IoT="none" NNm="FB1_PT6" SNm="FB1_PT6"/><Net IoT="none" NNm="FB1_PT7" SNm="FB1_PT7"/><Net IoT="none" NNm="FB1_PT8" SNm="FB1_PT8"/><Net IoT="none" NNm="FB1_PT9" SNm="FB1_PT9"/><Globals><GlblBuf Nm="GCK0" GType="GCK"><IPort NNm="FB2_5_I"/></GlblBuf></Globals><Lb Nm="FB1"><LbT Nm="FB1_PT0" PtT="XBR_CT_X"><OPort NNm="FB1_PT0"/><IPort NNm="FB1_16_Q"/><IPort NNm="FB1_14_Q"/><IPort NNm="FB1_15_Q"/></LbT><LbT Nm="FB1_PT1" PtT="XBR_CT_X"><OPort NNm="FB1_PT1"/><IPort NNm="FB1_16_Q"/><IPort NNm="FB1_14_Q"/><IPort NNm="FB1_15_Q"/></LbT><LbT Nm="FB1_PT2" PtT="XBR_CT_X"><OPort NNm="FB1_PT2"/><IPort NNm="FB1_16_Q"/><IPort NNm="FB1_14_Q"/><IPort NNm="FB1_1_Q"/></LbT><LbT Nm="FB1_PT3" PtT="XBR_CT_X"><OPort NNm="FB1_PT3"/><IPort NNm="FB1_16_Q"/><IPort NNm="FB1_14_Q"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_15_Q"/></LbT><LbT Nm="FB1_PT4" PtT="XBR_CT"><OPort NNm="FB1_PT4"/><IPort NNm="FB1_16_Q"/><IPort NNm="FB1_15_Q"/></LbT><LbT Nm="FB1_PT5" PtT="XBR_CT"><OPort NNm="FB1_PT5"/><IPort NNm="FB1_16_Q"/><IPort NNm="FB1_14_Q"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_15_Q"/></LbT><LbT Nm="FB1_PT6" PtT="XBR_CT"><OPort NNm="FB1_PT6"/><IPort NNm="FB1_16_Q"/><IPort NNm="FB1_14_Q"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_15_Q"/></LbT><LbT Nm="FB1_PT7" PtT="XBR_CT"><OPort NNm="FB1_PT7"/><IPort NNm="FB1_16_Q"/><IPort NNm="FB1_14_Q"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_15_Q"/></LbT><LbT Nm="FB1_PT8" PtT="XBR_A"><OPort NNm="FB1_PT8"/><IPort NNm="FB1_16_Q"/><IPort NNm="FB1_1_I"/><IPort NNm="FB1_14_Q"/><IPort NNm="FB1_1_Q"/></LbT><LbT Nm="FB1_PT9" PtT="XBR_B"><OPort NNm="FB1_PT9"/><IPort NNm="FB1_1_I"/><IPort NNm="FB1_14_Q"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_15_Q"/></LbT><LbT Nm="FB1_PT19" PtT="XBR_C"><OPort NNm="FB1_PT19"/><IPort NNm="FB1_16_Q"/><IPort NNm="FB1_14_Q"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_15_Q"/></LbT><LbT Nm="FB1_PT49" PtT="XBR_C"><OPort NNm="FB1_PT49"/><IPort NNm="FB1_1_I"/><IPort NNm="FB1_1_Q"/></LbT><LbT Nm="FB1_PT52" PtT="XBR_C"><OPort NNm="FB1_PT52"/><IPort NNm="FB1_16_Q"/><IPort NNm="FB1_1_I"/><IPort NNm="FB1_14_Q"/><IPort NNm="FB1_1_Q"/></LbT><Mc Nm="FB1_1"><ClkMux Nm="FB1_1_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_1_MC_CLK"/></ClkMux><FbMux Nm="FB1_1_N"><IPort NNm="FB1_1_Q"/></FbMux><FbMux Nm="FB1_1_P"><IPort NNm="FB1_1_I"/></FbMux><InBuf Nm="FB1_1_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="En"/><OPort NNm="FB1_1_I"/></InBuf><DFlop Nm="FB1_1_FF"><FlopPort NNm="FB1_1_I" Port="D"/><FlopPort NNm="FB1_1_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_1_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_2"><ClkMux Nm="FB1_2_MC_CLK" Rate="1"><IPort NNm="FB1_PT4"/><OPort NNm="FB1_2_MC_CLK"/></ClkMux><InBuf Nm="FB1_2_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="Date_out<1>"/></InBuf><OutBuf Nm="FB1_2_O" IOS="LVCMOS18"><IPort NNm="FB1_2_Q"/><OPort NNm="Date_out<1>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_2_FF"><FlopPort NNm="FB1_2_OR" Port="D"/><FlopPort NNm="FB1_2_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_2_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_2_OR"><OPort NNm="FB1_2_OR"/><IPort NNm="FB1_PT4"/><IPort NNm="FB1_PT5"/><IPort NNm="FB1_PT6"/></Or></Mc><Mc Nm="FB1_3"><ClkMux Nm="FB1_3_MC_CLK" Rate="1"><IPort NNm="FB1_PT4"/><OPort NNm="FB1_3_MC_CLK"/></ClkMux><InBuf Nm="FB1_3_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="Date_out<3>"/></InBuf><OutBuf Nm="FB1_3_O" IOS="LVCMOS18"><IPort NNm="FB1_3_Q"/><OPort NNm="Date_out<3>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_3_FF"><FlopPort NNm="FB1_3_OR" Port="D"/><FlopPort NNm="FB1_3_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_3_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_3_OR"><OPort NNm="FB1_3_OR"/><IPort NNm="FB1_PT4"/><IPort NNm="FB1_PT19"/><IPort NNm="FB1_PT7"/><IPort NNm="FB1_PT6"/></Or></Mc><Mc Nm="FB1_4"><ClkMux Nm="FB1_4_MC_CLK" Rate="1"><IPort NNm="FB1_PT4"/><OPort NNm="FB1_4_MC_CLK"/></ClkMux><XorMux Nm="FB1_4_AND"><IPort NNm="FB1_PT19"/></XorMux><InBuf Nm="FB1_4_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="Date_out<2>"/></InBuf><OutBuf Nm="FB1_4_O" IOS="LVCMOS18"><IPort NNm="FB1_4_Q"/><OPort NNm="Date_out<2>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_4_FF"><FlopPort NNm="FB1_PT19" Port="D"/><FlopPort NNm="FB1_4_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_4_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_5"><ClkMux Nm="FB1_5_MC_CLK" Rate="1"><IPort NNm="FB1_PT4"/><OPort NNm="FB1_5_MC_CLK"/></ClkMux><InBuf Nm="FB1_5_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="Date_out<0>"/></InBuf><OutBuf Nm="FB1_5_O" IOS="LVCMOS18"><IPort NNm="FB1_5_Q"/><OPort NNm="Date_out<0>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_5_FF"><FlopPort NNm="FB1_5_OR" Port="D"/><FlopPort NNm="FB1_5_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_5_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_5_OR"><OPort NNm="FB1_5_OR"/><IPort NNm="FB1_PT2"/><IPort NNm="FB1_PT1"/><IPort NNm="FB1_PT0"/><IPort NNm="FB1_PT3"/></Or></Mc><Mc Nm="FB1_6"/><Mc Nm="FB1_7"/><Mc Nm="FB1_8"/><Mc Nm="FB1_9"/><Mc Nm="FB1_10"/><Mc Nm="FB1_11"/><Mc Nm="FB1_12"/><Mc Nm="FB1_13"/><Mc Nm="FB1_14"><ClkMux Nm="FB1_14_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_14_MC_CLK"/></ClkMux><XorMux Nm="FB1_14_AND"><IPort NNm="FB1_PT49"/></XorMux><FbMux Nm="FB1_14_N"><IPort NNm="FB1_14_Q"/></FbMux><DFlop Nm="FB1_14_FF"><FlopPort NNm="FB1_PT49" Port="D"/><FlopPort NNm="FB1_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_14_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_15"><ClkMux Nm="FB1_15_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_15_MC_CLK"/></ClkMux><XorMux Nm="FB1_15_AND"><IPort NNm="FB1_PT52"/></XorMux><FbMux Nm="FB1_15_N"><IPort NNm="FB1_15_Q"/></FbMux><DFlop Nm="FB1_15_FF"><FlopPort NNm="FB1_PT52" Port="D"/><FlopPort NNm="FB1_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_15_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_16"><ClkMux Nm="FB1_16_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_16_MC_CLK"/></ClkMux><FbMux Nm="FB1_16_N"><IPort NNm="FB1_16_Q"/></FbMux><DFlop Nm="FB1_16_FF"><FlopPort NNm="FB1_16_OR" Port="D"/><FlopPort NNm="FB1_16_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_16_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_16_OR"><OPort NNm="FB1_16_OR"/><IPort NNm="FB1_PT8"/><IPort NNm="FB1_PT9"/></Or></Mc></Lb><Lb Nm="FB2"><Mc Nm="FB2_1"/><Mc Nm="FB2_2"/><Mc Nm="FB2_3"/><Mc Nm="FB2_4"/><Mc Nm="FB2_5"><InBuf Nm="FB2_5_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="clock"/><OPort NNm="FB2_5_I"/></InBuf></Mc><Mc Nm="FB2_6"/><Mc Nm="FB2_7"/><Mc Nm="FB2_8"/><Mc Nm="FB2_9"/><Mc Nm="FB2_10"/><Mc Nm="FB2_11"/><Mc Nm="FB2_12"/><Mc Nm="FB2_13"/><Mc Nm="FB2_14"/><Mc Nm="FB2_15"/><Mc Nm="FB2_16"/></Lb></Document>
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