ccdout.syr

CCD信号由于其特殊性,一般不能有信号源产生,本程序采用VHDL语言

Release 8.2i - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
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--> Reading design: CCDOUT.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "CCDOUT.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "CCDOUT"
Output Format                      : NGC
Target Device                      : Automotive CoolRunner2

---- Source Options
Top Module Name                    : CCDOUT
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : CCDOUT.lso
verilog2001                        : YES
safe_implementation                : No
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/MY_DESIGN/ISE/LXJ/CCDOUT/CCDOUT.vhd" in Library work.
Architecture behavioral of Entity ccdout is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <CCDOUT> in library <work> (architecture <behavioral>).

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <CCDOUT> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "D:/MY_DESIGN/ISE/LXJ/CCDOUT/CCDOUT.vhd" line 39: The following signals are missing in the process sensitivity list:
   cnt.
Entity <CCDOUT> analyzed. Unit <CCDOUT> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <CCDOUT>.
    Related source file is "D:/MY_DESIGN/ISE/LXJ/CCDOUT/CCDOUT.vhd".
    Found 12x4-bit ROM for signal <$mux0012>.
WARNING:Xst:737 - Found 4-bit latch for signal <Date_out>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
    Found 4-bit down counter for signal <cnt>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
Unit <CCDOUT> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 12x4-bit ROM                                          : 1
# Counters                                             : 1
 4-bit down counter                                    : 1
# Latches                                              : 1
 4-bit latch                                           : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 12x4-bit ROM                                          : 1
# Counters                                             : 1
 4-bit down counter                                    : 1
# Registers                                            : 4
 Flip-Flops                                            : 4
# Latches                                              : 1
 4-bit latch                                           : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <CCDOUT> ...
  implementation constraint: INIT=s	 : cnt_3
  implementation constraint: INIT=s	 : cnt_2
  implementation constraint: INIT=r	 : cnt_0
  implementation constraint: INIT=r	 : cnt_1

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : CCDOUT.ngr
Top Level Output File Name         : CCDOUT
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : Automotive CoolRunner2
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 6

Cell Usage :
# BELS                             : 70
#      AND2                        : 18
#      AND3                        : 4
#      AND4                        : 1
#      GND                         : 1
#      INV                         : 29
#      OR2                         : 10
#      OR3                         : 2
#      OR4                         : 1
#      XOR2                        : 4
# FlipFlops/Latches                : 8
#      FDCE                        : 4
#      LD                          : 4
# IO Buffers                       : 6
#      IBUF                        : 2
#      OBUF                        : 4
=========================================================================
CPU : 8.28 / 8.81 s | Elapsed : 8.00 / 9.00 s
 
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Total memory usage is 114832 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    1 (   0 filtered)