ccdout.gyd

CCD信号由于其特殊性,一般不能有信号源产生,本程序采用VHDL语言

Pin Freeze File:  version I.31

A2C32A44VQ XA2C32A-6-VQ44
En S:PIN38
clock S:PIN43
Date_out<0> S:PIN33
Date_out<1> S:PIN37
Date_out<2> S:PIN34
Date_out<3> S:PIN36


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.

PARTITION FB1_1 cnt<0> Date_out<1> Date_out<3> Date_out<2>
		 Date_out<0>
PARTITION FB1_14 cnt<1> cnt<3> cnt<2>