clk_divider.sym

CCD信号由于其特殊性,一般不能有信号源产生,本程序采用VHDL语言

VERSION 5
BEGIN SYMBOL clk_divider
SYMBOLTYPE BLOCK
TIMESTAMP 2007 5 10 4 10 34
SYMPIN 0 -160 Input clk
SYMPIN 0 -96 Input PinName
SYMPIN 0 -32 Input reset
RECTANGLE N 48 -192 304 0 
BEGIN DISPLAY 176 -200 ATTR SymbolName
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
LINE N 48 -160 0 -160 
BEGIN DISPLAY 56 -160 PIN clk ATTR PinName
    FONT 8 "Arial"
END DISPLAY
LINE N 48 -96 0 -96 
BEGIN DISPLAY 56 -96 PIN PinName ATTR PinName
    FONT 8 "Arial"
END DISPLAY
LINE N 48 -32 0 -32 
BEGIN DISPLAY 56 -32 PIN reset ATTR PinName
    FONT 8 "Arial"
END DISPLAY
END SYMBOL