_primary.vhd

来自「这是一个IIC的接口程序」· VHDL 代码 · 共 19 行

library verilog;
use verilog.vl_types.all;
entity tst_bench_top is
    generic(
        PRER_LO         : integer := 0;
        PRER_HI         : integer := 1;
        CTR             : integer := 2;
        RXR             : integer := 3;
        TXR             : integer := 3;
        CR              : integer := 4;
        SR              : integer := 4;
        TXR_R           : integer := 5;
        CR_R            : integer := 6;
        RD              : integer := 1;
        WR              : integer := 0;
        SADR            : integer := 16
    );
end tst_bench_top;