_primary.vhd

来自「这是一个IIC的接口程序」· VHDL 代码 · 共 7 行

library verilog;
use verilog.vl_types.all;
entity MAXII_PRIM_DFFE is
    // This module cannot be connected to from
    // VHDL because it has unnamed ports.
end MAXII_PRIM_DFFE;