display.map.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 18 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 16 22:49:48 2006 " "Info: Processing started: Sun Apr 16 22:49:48 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off display -c display " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off display -c display" {  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/DDS/10k844/display/freq4/display.vhd " "Warning: Can't analyze file -- file D:/DDS/10k844/display/freq4/display.vhd is missing" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "display.vhd 2 1 " "Info: Using design file display.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display-behav " "Info: Found design unit 1: display-behav" {  } { { "display.vhd" "" { Text "E:/EDA/DDS/display/freq4/display.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "display.vhd" "" { Text "E:/EDA/DDS/display/freq4/display.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "display " "Info: Elaborating entity \"display\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "ctr.vhd 2 1 " "Info: Using design file ctr.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CTR-BEHAV " "Info: Found design unit 1: CTR-BEHAV" {  } { { "ctr.vhd" "" { Text "E:/EDA/DDS/display/freq4/ctr.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 CTR " "Info: Found entity 1: CTR" {  } { { "ctr.vhd" "" { Text "E:/EDA/DDS/display/freq4/ctr.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ctr ctr:u1 " "Info: Elaborating entity \"ctr\" for hierarchy \"ctr:u1\"" {  } { { "display.vhd" "u1" { Text "E:/EDA/DDS/display/freq4/display.vhd" 33 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "conter4.vhd 2 1 " "Info: Using design file conter4.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 conter4-behav " "Info: Found design unit 1: conter4-behav" {  } { { "conter4.vhd" "" { Text "E:/EDA/DDS/display/freq4/conter4.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 conter4 " "Info: Found entity 1: conter4" {  } { { "conter4.vhd" "" { Text "E:/EDA/DDS/display/freq4/conter4.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "conter4 conter4:u2 " "Info: Elaborating entity \"conter4\" for hierarchy \"conter4:u2\"" {  } { { "display.vhd" "u2" { Text "E:/EDA/DDS/display/freq4/display.vhd" 34 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "reg16b.vhd 2 1 " "Info: Using design file reg16b.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg16b-BEHAV " "Info: Found design unit 1: reg16b-BEHAV" {  } { { "reg16b.vhd" "" { Text "E:/EDA/DDS/display/freq4/reg16b.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 reg16b " "Info: Found entity 1: reg16b" {  } { { "reg16b.vhd" "" { Text "E:/EDA/DDS/display/freq4/reg16b.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg16b reg16b:u3 " "Info: Elaborating entity \"reg16b\" for hierarchy \"reg16b:u3\"" {  } { { "display.vhd" "u3" { Text "E:/EDA/DDS/display/freq4/display.vhd" 35 -1 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "4 " "Info: Inferred 4 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "conter4:u2\|CQI1\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"conter4:u2\|CQI1\[0\]~4\"" {  } { { "conter4.vhd" "CQI1\[0\]~4" { Text "E:/EDA/DDS/display/freq4/conter4.vhd" 12 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "conter4:u2\|CQI2\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"conter4:u2\|CQI2\[0\]~8\"" {  } { { "conter4.vhd" "CQI2\[0\]~8" { Text "E:/EDA/DDS/display/freq4/conter4.vhd" 13 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "conter4:u2\|CQI3\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"conter4:u2\|CQI3\[0\]~8\"" {  } { { "conter4.vhd" "CQI3\[0\]~8" { Text "E:/EDA/DDS/display/freq4/conter4.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "conter4:u2\|CQI4\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"conter4:u2\|CQI4\[0\]~8\"" {  } { { "conter4.vhd" "CQI4\[0\]~8" { Text "E:/EDA/DDS/display/freq4/conter4.vhd" 15 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "63 " "Info: Implemented 63 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "45 " "Info: Implemented 45 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 16 22:49:54 2006 " "Info: Processing ended: Sun Apr 16 22:49:54 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}