display.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 12 行 · 第 1/3 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Fin register conter4:u2\|lpm_counter:CQI1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] register conter4:u2\|lpm_counter:CQI4_rtl_3\|alt_counter_f10ke:wysi_counter\|q\[3\] 43.86 MHz 22.8 ns Internal " "Info: Clock \"Fin\" has Internal fmax of 43.86 MHz between source register \"conter4:u2\|lpm_counter:CQI1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]\" and destination register \"conter4:u2\|lpm_counter:CQI4_rtl_3\|alt_counter_f10ke:wysi_counter\|q\[3\]\" (period= 22.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.200 ns + Longest register register " "Info: + Longest register to register delay is 19.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns conter4:u2\|lpm_counter:CQI1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 1 REG LC6_A14 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A14; Fanout = 5; REG Node = 'conter4:u2\|lpm_counter:CQI1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "" { conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns conter4:u2\|lpm_counter:CQI1_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[2\]~58 2 COMB LC2_A14 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC2_A14; Fanout = 1; COMB Node = 'conter4:u2\|lpm_counter:CQI1_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[2\]~58'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "2.900 ns" { conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~58 } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 5.300 ns conter4:u2\|lpm_counter:CQI1_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~1 3 COMB LC1_A14 16 " "Info: 3: + IC(0.600 ns) + CELL(1.800 ns) = 5.300 ns; Loc. = LC1_A14; Fanout = 16; COMB Node = 'conter4:u2\|lpm_counter:CQI1_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~1'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "2.400 ns" { conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~58 conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.300 ns) 9.900 ns conter4:u2\|CQI4\[0\]~39 4 COMB LC2_A13 16 " "Info: 4: + IC(2.300 ns) + CELL(2.300 ns) = 9.900 ns; Loc. = LC2_A13; Fanout = 16; COMB Node = 'conter4:u2\|CQI4\[0\]~39'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "4.600 ns" { conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 conter4:u2|CQI4[0]~39 } "NODE_NAME" } "" } } { "conter4.vhd" "" { Text "E:/EDA/DDS/display/freq4/conter4.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 12.300 ns conter4:u2\|CQI4\[0\]~40 5 COMB LC1_A13 16 " "Info: 5: + IC(0.600 ns) + CELL(1.800 ns) = 12.300 ns; Loc. = LC1_A13; Fanout = 16; COMB Node = 'conter4:u2\|CQI4\[0\]~40'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "2.400 ns" { conter4:u2|CQI4[0]~39 conter4:u2|CQI4[0]~40 } "NODE_NAME" } "" } } { "conter4.vhd" "" { Text "E:/EDA/DDS/display/freq4/conter4.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.300 ns) 16.900 ns conter4:u2\|lpm_counter:CQI4_rtl_3\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~1 6 COMB LC2_A23 7 " "Info: 6: + IC(2.300 ns) + CELL(2.300 ns) = 16.900 ns; Loc. = LC2_A23; Fanout = 7; COMB Node = 'conter4:u2\|lpm_counter:CQI4_rtl_3\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~1'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "4.600 ns" { conter4:u2|CQI4[0]~40 conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 19.200 ns conter4:u2\|lpm_counter:CQI4_rtl_3\|alt_counter_f10ke:wysi_counter\|q\[3\] 7 REG LC8_A23 3 " "Info: 7: + IC(0.600 ns) + CELL(1.700 ns) = 19.200 ns; Loc. = LC8_A23; Fanout = 3; REG Node = 'conter4:u2\|lpm_counter:CQI4_rtl_3\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "2.300 ns" { conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.200 ns 63.54 % " "Info: Total cell delay = 12.200 ns ( 63.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns 36.46 % " "Info: Total interconnect delay = 7.000 ns ( 36.46 % )" {  } {  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "19.200 ns" { conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~58 conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 conter4:u2|CQI4[0]~39 conter4:u2|CQI4[0]~40 conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "19.200 ns" { conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~58 conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 conter4:u2|CQI4[0]~39 conter4:u2|CQI4[0]~40 conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.600ns 0.600ns 2.300ns 0.600ns 2.300ns 0.600ns } { 0.000ns 2.300ns 1.800ns 2.300ns 1.800ns 2.300ns 1.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Fin destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"Fin\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Fin 1 CLK PIN_2 28 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_2; Fanout = 28; CLK Node = 'Fin'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "" { Fin } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/EDA/DDS/display/freq4/display.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns conter4:u2\|lpm_counter:CQI4_rtl_3\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC8_A23 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_A23; Fanout = 3; REG Node = 'conter4:u2\|lpm_counter:CQI4_rtl_3\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "2.500 ns" { Fin conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "5.300 ns" { Fin conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { Fin Fin~out conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Fin source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"Fin\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Fin 1 CLK PIN_2 28 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_2; Fanout = 28; CLK Node = 'Fin'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "" { Fin } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/EDA/DDS/display/freq4/display.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns conter4:u2\|lpm_counter:CQI1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC6_A14 5 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_A14; Fanout = 5; REG Node = 'conter4:u2\|lpm_counter:CQI1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "2.500 ns" { Fin conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "5.300 ns" { Fin conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { Fin Fin~out conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "5.300 ns" { Fin conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { Fin Fin~out conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "5.300 ns" { Fin conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { Fin Fin~out conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "19.200 ns" { conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~58 conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 conter4:u2|CQI4[0]~39 conter4:u2|CQI4[0]~40 conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "19.200 ns" { conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~58 conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 conter4:u2|CQI4[0]~39 conter4:u2|CQI4[0]~40 conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.600ns 0.600ns 2.300ns 0.600ns 2.300ns 0.600ns } { 0.000ns 2.300ns 1.800ns 2.300ns 1.800ns 2.300ns 1.700ns } } } { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "5.300 ns" { Fin conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { Fin Fin~out conter4:u2|lpm_counter:CQI4_rtl_3|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "5.300 ns" { Fin conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { Fin Fin~out conter4:u2|lpm_counter:CQI1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock displayout\[5\] reg16b:u3\|q\[5\] 19.800 ns register " "Info: tco from clock \"clock\" to destination pin \"displayout\[5\]\" through register \"reg16b:u3\|q\[5\]\" is 19.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 11.000 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'clock'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "" { clock } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/EDA/DDS/display/freq4/display.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns CTR:u1\|CNT_EN 2 REG LC1_B11 33 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B11; Fanout = 33; REG Node = 'CTR:u1\|CNT_EN'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "3.600 ns" { clock CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "ctr.vhd" "" { Text "E:/EDA/DDS/display/freq4/ctr.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 11.000 ns reg16b:u3\|q\[5\] 3 REG LC1_A16 1 " "Info: 3: + IC(4.600 ns) + CELL(0.000 ns) = 11.000 ns; Loc. = LC1_A16; Fanout = 1; REG Node = 'reg16b:u3\|q\[5\]'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "4.600 ns" { CTR:u1|CNT_EN reg16b:u3|q[5] } "NODE_NAME" } "" } } { "reg16b.vhd" "" { Text "E:/EDA/DDS/display/freq4/reg16b.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 35.45 % " "Info: Total cell delay = 3.900 ns ( 35.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns 64.55 % " "Info: Total interconnect delay = 7.100 ns ( 64.55 % )" {  } {  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "11.000 ns" { clock CTR:u1|CNT_EN reg16b:u3|q[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out CTR:u1|CNT_EN reg16b:u3|q[5] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "reg16b.vhd" "" { Text "E:/EDA/DDS/display/freq4/reg16b.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.700 ns + Longest register pin " "Info: + Longest register to pin delay is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg16b:u3\|q\[5\] 1 REG LC1_A16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A16; Fanout = 1; REG Node = 'reg16b:u3\|q\[5\]'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "" { reg16b:u3|q[5] } "NODE_NAME" } "" } } { "reg16b.vhd" "" { Text "E:/EDA/DDS/display/freq4/reg16b.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(5.100 ns) 7.700 ns displayout\[5\] 2 PIN PIN_62 0 " "Info: 2: + IC(2.600 ns) + CELL(5.100 ns) = 7.700 ns; Loc. = PIN_62; Fanout = 0; PIN Node = 'displayout\[5\]'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "7.700 ns" { reg16b:u3|q[5] displayout[5] } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/EDA/DDS/display/freq4/display.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns 66.23 % " "Info: Total cell delay = 5.100 ns ( 66.23 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 33.77 % " "Info: Total interconnect delay = 2.600 ns ( 33.77 % )" {  } {  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "7.700 ns" { reg16b:u3|q[5] displayout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.700 ns" { reg16b:u3|q[5] displayout[5] } { 0.000ns 2.600ns } { 0.000ns 5.100ns } } }  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "11.000 ns" { clock CTR:u1|CNT_EN reg16b:u3|q[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out CTR:u1|CNT_EN reg16b:u3|q[5] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "7.700 ns" { reg16b:u3|q[5] displayout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.700 ns" { reg16b:u3|q[5] displayout[5] } { 0.000ns 2.600ns } { 0.000ns 5.100ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 16 22:50:13 2006 " "Info: Processing ended: Sun Apr 16 22:50:13 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}