display.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 12 行 · 第 1/3 页

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "display.vhd" "" { Text "E:/EDA/DDS/display/freq4/display.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Fin " "Info: Assuming node \"Fin\" is an undefined clock" {  } { { "display.vhd" "" { Text "E:/EDA/DDS/display/freq4/display.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Fin" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CTR:u1\|CNT_EN " "Info: Detected ripple clock \"CTR:u1\|CNT_EN\" as buffer" {  } { { "ctr.vhd" "" { Text "E:/EDA/DDS/display/freq4/ctr.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CTR:u1\|CNT_EN" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock register register CTR:u1\|CNT_EN CTR:u1\|CNT_EN 125.0 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 125.0 MHz between source register \"CTR:u1\|CNT_EN\" and destination register \"CTR:u1\|CNT_EN\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Longest register register " "Info: + Longest register to register delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CTR:u1\|CNT_EN 1 REG LC1_B11 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B11; Fanout = 33; REG Node = 'CTR:u1\|CNT_EN'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "" { CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "ctr.vhd" "" { Text "E:/EDA/DDS/display/freq4/ctr.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 1.800 ns CTR:u1\|CNT_EN 2 REG LC1_B11 33 " "Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC1_B11; Fanout = 33; REG Node = 'CTR:u1\|CNT_EN'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "1.800 ns" { CTR:u1|CNT_EN CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "ctr.vhd" "" { Text "E:/EDA/DDS/display/freq4/ctr.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns 66.67 % " "Info: Total cell delay = 1.200 ns ( 66.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 33.33 % " "Info: Total interconnect delay = 0.600 ns ( 33.33 % )" {  } {  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "1.800 ns" { CTR:u1|CNT_EN CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.800 ns" { CTR:u1|CNT_EN CTR:u1|CNT_EN } { 0.000ns 0.600ns } { 0.000ns 1.200ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'clock'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "" { clock } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/EDA/DDS/display/freq4/display.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns CTR:u1\|CNT_EN 2 REG LC1_B11 33 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B11; Fanout = 33; REG Node = 'CTR:u1\|CNT_EN'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "2.500 ns" { clock CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "ctr.vhd" "" { Text "E:/EDA/DDS/display/freq4/ctr.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "5.300 ns" { clock CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out CTR:u1|CNT_EN } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'clock'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "" { clock } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/EDA/DDS/display/freq4/display.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns CTR:u1\|CNT_EN 2 REG LC1_B11 33 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B11; Fanout = 33; REG Node = 'CTR:u1\|CNT_EN'" {  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "2.500 ns" { clock CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "ctr.vhd" "" { Text "E:/EDA/DDS/display/freq4/ctr.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "5.300 ns" { clock CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out CTR:u1|CNT_EN } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "5.300 ns" { clock CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out CTR:u1|CNT_EN } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "5.300 ns" { clock CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out CTR:u1|CNT_EN } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "ctr.vhd" "" { Text "E:/EDA/DDS/display/freq4/ctr.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "ctr.vhd" "" { Text "E:/EDA/DDS/display/freq4/ctr.vhd" 6 -1 0 } }  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "1.800 ns" { CTR:u1|CNT_EN CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.800 ns" { CTR:u1|CNT_EN CTR:u1|CNT_EN } { 0.000ns 0.600ns } { 0.000ns 1.200ns } } } { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "5.300 ns" { clock CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out CTR:u1|CNT_EN } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "5.300 ns" { clock CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out CTR:u1|CNT_EN } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" "" { Report "E:/EDA/DDS/display/freq4/db/display_cmp.qrpt" Compiler "display" "UNKNOWN" "V1" "E:/EDA/DDS/display/freq4/db/display.quartus_db" { Floorplan "E:/EDA/DDS/display/freq4/" "" "" { CTR:u1|CNT_EN } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { CTR:u1|CNT_EN } {  } {  } } } { "ctr.vhd" "" { Text "E:/EDA/DDS/display/freq4/ctr.vhd" 6 -1 0 } }  } 0}