init_cnt8b.fit.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 38 行 · 第 1/2 页

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "17 unused 3.30 8 9 0 " "Info: Number of I/O pins in group: 17 (unused VREF, 3.30 VCCIO, 8 input, 9 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 19 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  19 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 26 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.239 ns register register " "Info: Estimated most critical path is register to register delay of 5.239 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT8\[1\] 1 REG LAB_X1_Y5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X1_Y5; Fanout = 4; REG Node = 'CNT8\[1\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "" { CNT8[1] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.698 ns) + CELL(0.575 ns) 1.273 ns add~184COUT1_219 2 COMB LAB_X2_Y5 2 " "Info: 2: + IC(0.698 ns) + CELL(0.575 ns) = 1.273 ns; Loc. = LAB_X2_Y5; Fanout = 2; COMB Node = 'add~184COUT1_219'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "1.273 ns" { CNT8[1] add~184COUT1_219 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.353 ns add~189COUT1_220 3 COMB LAB_X2_Y5 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.353 ns; Loc. = LAB_X2_Y5; Fanout = 2; COMB Node = 'add~189COUT1_220'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "0.080 ns" { add~184COUT1_219 add~189COUT1_220 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.433 ns add~194COUT1 4 COMB LAB_X2_Y5 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.433 ns; Loc. = LAB_X2_Y5; Fanout = 2; COMB Node = 'add~194COUT1'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "0.080 ns" { add~189COUT1_220 add~194COUT1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.691 ns add~199 5 COMB LAB_X2_Y5 3 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.691 ns; Loc. = LAB_X2_Y5; Fanout = 3; COMB Node = 'add~199'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "0.258 ns" { add~194COUT1 add~199 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.370 ns add~202 6 COMB LAB_X2_Y5 2 " "Info: 6: + IC(0.000 ns) + CELL(0.679 ns) = 2.370 ns; Loc. = LAB_X2_Y5; Fanout = 2; COMB Node = 'add~202'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "0.679 ns" { add~199 add~202 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.777 ns) + CELL(0.114 ns) 3.261 ns reduce_nor~41 7 COMB LAB_X1_Y5 1 " "Info: 7: + IC(0.777 ns) + CELL(0.114 ns) = 3.261 ns; Loc. = LAB_X1_Y5; Fanout = 1; COMB Node = 'reduce_nor~41'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "0.891 ns" { add~202 reduce_nor~41 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.442 ns) 4.153 ns reduce_nor~0 8 COMB LAB_X2_Y5 9 " "Info: 8: + IC(0.450 ns) + CELL(0.442 ns) = 4.153 ns; Loc. = LAB_X2_Y5; Fanout = 9; COMB Node = 'reduce_nor~0'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "0.892 ns" { reduce_nor~41 reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.777 ns) + CELL(0.309 ns) 5.239 ns CNT8\[1\] 9 REG LAB_X1_Y5 4 " "Info: 9: + IC(0.777 ns) + CELL(0.309 ns) = 5.239 ns; Loc. = LAB_X1_Y5; Fanout = 4; REG Node = 'CNT8\[1\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "1.086 ns" { reduce_nor~0 CNT8[1] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.537 ns 48.43 % " "Info: Total cell delay = 2.537 ns ( 48.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.702 ns 51.57 % " "Info: Total interconnect delay = 2.702 ns ( 51.57 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "5.239 ns" { CNT8[1] add~184COUT1_219 add~189COUT1_220 add~194COUT1 add~199 add~202 reduce_nor~41 reduce_nor~0 CNT8[1] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 11 20:08:58 2006 " "Info: Processing ended: Tue Apr 11 20:08:58 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}