init_cnt8b.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 10 行 · 第 1/3 页

QMSG
10 行
字号
123
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register CNT8\[0\] register CNT8\[4\] 161.06 MHz 6.209 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 161.06 MHz between source register \"CNT8\[0\]\" and destination register \"CNT8\[4\]\" (period= 6.209 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.948 ns + Longest register register " "Info: + Longest register to register delay is 5.948 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT8\[0\] 1 REG LC_X2_Y5_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y5_N9; Fanout = 4; REG Node = 'CNT8\[0\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "" { CNT8[0] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.531 ns) + CELL(0.575 ns) 1.106 ns add~179COUT1_218 2 COMB LC_X2_Y5_N0 2 " "Info: 2: + IC(0.531 ns) + CELL(0.575 ns) = 1.106 ns; Loc. = LC_X2_Y5_N0; Fanout = 2; COMB Node = 'add~179COUT1_218'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "1.106 ns" { CNT8[0] add~179COUT1_218 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.186 ns add~184COUT1_219 3 COMB LC_X2_Y5_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.186 ns; Loc. = LC_X2_Y5_N1; Fanout = 2; COMB Node = 'add~184COUT1_219'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "0.080 ns" { add~179COUT1_218 add~184COUT1_219 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.266 ns add~189COUT1_220 4 COMB LC_X2_Y5_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.266 ns; Loc. = LC_X2_Y5_N2; Fanout = 2; COMB Node = 'add~189COUT1_220'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "0.080 ns" { add~184COUT1_219 add~189COUT1_220 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 1.874 ns add~192 5 COMB LC_X2_Y5_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.608 ns) = 1.874 ns; Loc. = LC_X2_Y5_N3; Fanout = 2; COMB Node = 'add~192'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "0.608 ns" { add~189COUT1_220 add~192 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.727 ns) + CELL(0.590 ns) 3.191 ns reduce_nor~40 6 COMB LC_X1_Y5_N0 1 " "Info: 6: + IC(0.727 ns) + CELL(0.590 ns) = 3.191 ns; Loc. = LC_X1_Y5_N0; Fanout = 1; COMB Node = 'reduce_nor~40'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "1.317 ns" { add~192 reduce_nor~40 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.664 ns) + CELL(0.442 ns) 4.297 ns reduce_nor~0 7 COMB LC_X2_Y5_N8 9 " "Info: 7: + IC(0.664 ns) + CELL(0.442 ns) = 4.297 ns; Loc. = LC_X2_Y5_N8; Fanout = 9; COMB Node = 'reduce_nor~0'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "1.106 ns" { reduce_nor~40 reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.913 ns) + CELL(0.738 ns) 5.948 ns CNT8\[4\] 8 REG LC_X1_Y5_N3 3 " "Info: 8: + IC(0.913 ns) + CELL(0.738 ns) = 5.948 ns; Loc. = LC_X1_Y5_N3; Fanout = 3; REG Node = 'CNT8\[4\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "1.651 ns" { reduce_nor~0 CNT8[4] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.113 ns 52.34 % " "Info: Total cell delay = 3.113 ns ( 52.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.835 ns 47.66 % " "Info: Total interconnect delay = 2.835 ns ( 47.66 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "5.948 ns" { CNT8[0] add~179COUT1_218 add~184COUT1_219 add~189COUT1_220 add~192 reduce_nor~40 reduce_nor~0 CNT8[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.948 ns" { CNT8[0] add~179COUT1_218 add~184COUT1_219 add~189COUT1_220 add~192 reduce_nor~40 reduce_nor~0 CNT8[4] } { 0.000ns 0.531ns 0.000ns 0.000ns 0.000ns 0.727ns 0.664ns 0.913ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.608ns 0.590ns 0.442ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "" { CLK } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns CNT8\[4\] 2 REG LC_X1_Y5_N3 3 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y5_N3; Fanout = 3; REG Node = 'CNT8\[4\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "1.261 ns" { CLK CNT8[4] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "2.730 ns" { CLK CNT8[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 CNT8[4] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.730 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "" { CLK } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns CNT8\[0\] 2 REG LC_X2_Y5_N9 4 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y5_N9; Fanout = 4; REG Node = 'CNT8\[0\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "1.261 ns" { CLK CNT8[0] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "2.730 ns" { CLK CNT8[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 CNT8[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "2.730 ns" { CLK CNT8[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 CNT8[4] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "2.730 ns" { CLK CNT8[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 CNT8[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "5.948 ns" { CNT8[0] add~179COUT1_218 add~184COUT1_219 add~189COUT1_220 add~192 reduce_nor~40 reduce_nor~0 CNT8[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.948 ns" { CNT8[0] add~179COUT1_218 add~184COUT1_219 add~189COUT1_220 add~192 reduce_nor~40 reduce_nor~0 CNT8[4] } { 0.000ns 0.531ns 0.000ns 0.000ns 0.000ns 0.727ns 0.664ns 0.913ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.608ns 0.590ns 0.442ns 0.738ns } } } { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "2.730 ns" { CLK CNT8[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 CNT8[4] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "2.730 ns" { CLK CNT8[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 CNT8[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "CNT8\[7\] DATA\[7\] CLK 4.822 ns register " "Info: tsu for register \"CNT8\[7\]\" (data pin = \"DATA\[7\]\", clock pin = \"CLK\") is 4.822 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.515 ns + Longest pin register " "Info: + Longest pin to register delay is 7.515 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DATA\[7\] 1 PIN PIN_7 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_7; Fanout = 1; PIN Node = 'DATA\[7\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "" { DATA[7] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.308 ns) + CELL(0.738 ns) 7.515 ns CNT8\[7\] 2 REG LC_X1_Y5_N6 2 " "Info: 2: + IC(5.308 ns) + CELL(0.738 ns) = 7.515 ns; Loc. = LC_X1_Y5_N6; Fanout = 2; REG Node = 'CNT8\[7\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "6.046 ns" { DATA[7] CNT8[7] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns 29.37 % " "Info: Total cell delay = 2.207 ns ( 29.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.308 ns 70.63 % " "Info: Total interconnect delay = 5.308 ns ( 70.63 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "7.515 ns" { DATA[7] CNT8[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.515 ns" { DATA[7] DATA[7]~out0 CNT8[7] } { 0.000ns 0.000ns 5.308ns } { 0.000ns 1.469ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.730 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "" { CLK } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns CNT8\[7\] 2 REG LC_X1_Y5_N6 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y5_N6; Fanout = 2; REG Node = 'CNT8\[7\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "1.261 ns" { CLK CNT8[7] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "2.730 ns" { CLK CNT8[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 CNT8[7] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "7.515 ns" { DATA[7] CNT8[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.515 ns" { DATA[7] DATA[7]~out0 CNT8[7] } { 0.000ns 0.000ns 5.308ns } { 0.000ns 1.469ns 0.738ns } } } { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "2.730 ns" { CLK CNT8[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 CNT8[7] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK FOUT\[0\] CNT8\[0\] 7.246 ns register " "Info: tco from clock \"CLK\" to destination pin \"FOUT\[0\]\" through register \"CNT8\[0\]\" is 7.246 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.730 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "" { CLK } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns CNT8\[0\] 2 REG LC_X2_Y5_N9 4 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y5_N9; Fanout = 4; REG Node = 'CNT8\[0\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "1.261 ns" { CLK CNT8[0] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "2.730 ns" { CLK CNT8[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 CNT8[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.292 ns + Longest register pin " "Info: + Longest register to pin delay is 4.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT8\[0\] 1 REG LC_X2_Y5_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y5_N9; Fanout = 4; REG Node = 'CNT8\[0\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "" { CNT8[0] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.184 ns) + CELL(2.108 ns) 4.292 ns FOUT\[0\] 2 PIN PIN_40 0 " "Info: 2: + IC(2.184 ns) + CELL(2.108 ns) = 4.292 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'FOUT\[0\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "4.292 ns" { CNT8[0] FOUT[0] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 49.11 % " "Info: Total cell delay = 2.108 ns ( 49.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.184 ns 50.89 % " "Info: Total interconnect delay = 2.184 ns ( 50.89 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "4.292 ns" { CNT8[0] FOUT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.292 ns" { CNT8[0] FOUT[0] } { 0.000ns 2.184ns } { 0.000ns 2.108ns } } }  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "2.730 ns" { CLK CNT8[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 CNT8[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "4.292 ns" { CNT8[0] FOUT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.292 ns" { CNT8[0] FOUT[0] } { 0.000ns 2.184ns } { 0.000ns 2.108ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "CNT8\[5\] DATA\[5\] CLK -4.248 ns register " "Info: th for register \"CNT8\[5\]\" (data pin = \"DATA\[5\]\", clock pin = \"CLK\") is -4.248 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.730 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "" { CLK } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns CNT8\[5\] 2 REG LC_X1_Y5_N2 4 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y5_N2; Fanout = 4; REG Node = 'CNT8\[5\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "1.261 ns" { CLK CNT8[5] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "2.730 ns" { CLK CNT8[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 CNT8[5] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.993 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.993 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DATA\[5\] 1 PIN PIN_33 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_33; Fanout = 1; PIN Node = 'DATA\[5\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "" { DATA[5] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.046 ns) + CELL(0.478 ns) 6.993 ns CNT8\[5\] 2 REG LC_X1_Y5_N2 4 " "Info: 2: + IC(5.046 ns) + CELL(0.478 ns) = 6.993 ns; Loc. = LC_X1_Y5_N2; Fanout = 4; REG Node = 'CNT8\[5\]'" {  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "5.524 ns" { DATA[5] CNT8[5] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/init_cnt8b/INIT_CNT8B.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns 27.84 % " "Info: Total cell delay = 1.947 ns ( 27.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.046 ns 72.16 % " "Info: Total interconnect delay = 5.046 ns ( 72.16 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "6.993 ns" { DATA[5] CNT8[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.993 ns" { DATA[5] DATA[5]~out0 CNT8[5] } { 0.000ns 0.000ns 5.046ns } { 0.000ns 1.469ns 0.478ns } } }  } 0}  } { { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "2.730 ns" { CLK CNT8[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { CLK CLK~out0 CNT8[5] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/init_cnt8b/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/init_cnt8b/" "" "6.993 ns" { DATA[5] CNT8[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.993 ns" { DATA[5] DATA[5]~out0 CNT8[5] } { 0.000ns 0.000ns 5.046ns } { 0.000ns 1.469ns 0.478ns } } }  } 0}
123

init_cnt8b.tan.qmsg - 源码说明

本页面展示了「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」中的 init_cnt8b.tan.qmsg 源码文件，采用 QMSG 编程语言编写，共 10 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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