cnt8b.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 10 行 · 第 1/2 页

{ "Info" "ITDB_TSU_RESULT" "Q1\[0\] EN CLK 4.982 ns register " "Info: tsu for register \"Q1\[0\]\" (data pin = \"EN\", clock pin = \"CLK\") is 4.982 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.712 ns + Longest pin register " "Info: + Longest pin to register delay is 7.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns EN 1 PIN PIN_6 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_6; Fanout = 9; PIN Node = 'EN'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { EN } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.376 ns) + CELL(0.867 ns) 7.712 ns Q1\[0\] 2 REG LC_X2_Y13_N0 5 " "Info: 2: + IC(5.376 ns) + CELL(0.867 ns) = 7.712 ns; Loc. = LC_X2_Y13_N0; Fanout = 5; REG Node = 'Q1\[0\]'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "6.243 ns" { EN Q1[0] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 30.29 % " "Info: Total cell delay = 2.336 ns ( 30.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.376 ns 69.71 % " "Info: Total interconnect delay = 5.376 ns ( 69.71 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "7.712 ns" { EN Q1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.712 ns" { EN EN~out0 Q1[0] } { 0.000ns 0.000ns 5.376ns } { 0.000ns 1.469ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.767 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns Q1\[0\] 2 REG LC_X2_Y13_N0 5 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X2_Y13_N0; Fanout = 5; REG Node = 'Q1\[0\]'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "1.298 ns" { CLK Q1[0] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 78.79 % " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns 21.21 % " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.767 ns" { CLK Q1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 Q1[0] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "7.712 ns" { EN Q1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.712 ns" { EN EN~out0 Q1[0] } { 0.000ns 0.000ns 5.376ns } { 0.000ns 1.469ns 0.867ns } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.767 ns" { CLK Q1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 Q1[0] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q\[4\] Q1\[4\] 6.964 ns register " "Info: tco from clock \"CLK\" to destination pin \"Q\[4\]\" through register \"Q1\[4\]\" is 6.964 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.767 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns Q1\[4\] 2 REG LC_X2_Y13_N4 4 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X2_Y13_N4; Fanout = 4; REG Node = 'Q1\[4\]'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "1.298 ns" { CLK Q1[4] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 78.79 % " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns 21.21 % " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.767 ns" { CLK Q1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 Q1[4] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.973 ns + Longest register pin " "Info: + Longest register to pin delay is 3.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q1\[4\] 1 REG LC_X2_Y13_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y13_N4; Fanout = 4; REG Node = 'Q1\[4\]'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { Q1[4] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.849 ns) + CELL(2.124 ns) 3.973 ns Q\[4\] 2 PIN PIN_3 0 " "Info: 2: + IC(1.849 ns) + CELL(2.124 ns) = 3.973 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'Q\[4\]'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "3.973 ns" { Q1[4] Q[4] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 53.46 % " "Info: Total cell delay = 2.124 ns ( 53.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.849 ns 46.54 % " "Info: Total interconnect delay = 1.849 ns ( 46.54 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "3.973 ns" { Q1[4] Q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.973 ns" { Q1[4] Q[4] } { 0.000ns 1.849ns } { 0.000ns 2.124ns } } }  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.767 ns" { CLK Q1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 Q1[4] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "3.973 ns" { Q1[4] Q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.973 ns" { Q1[4] Q[4] } { 0.000ns 1.849ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "Q1\[0\] EN CLK -4.930 ns register " "Info: th for register \"Q1\[0\]\" (data pin = \"EN\", clock pin = \"CLK\") is -4.930 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.767 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns Q1\[0\] 2 REG LC_X2_Y13_N0 5 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X2_Y13_N0; Fanout = 5; REG Node = 'Q1\[0\]'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "1.298 ns" { CLK Q1[0] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 78.79 % " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns 21.21 % " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.767 ns" { CLK Q1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 Q1[0] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.712 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns EN 1 PIN PIN_6 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_6; Fanout = 9; PIN Node = 'EN'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { EN } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.376 ns) + CELL(0.867 ns) 7.712 ns Q1\[0\] 2 REG LC_X2_Y13_N0 5 " "Info: 2: + IC(5.376 ns) + CELL(0.867 ns) = 7.712 ns; Loc. = LC_X2_Y13_N0; Fanout = 5; REG Node = 'Q1\[0\]'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "6.243 ns" { EN Q1[0] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 30.29 % " "Info: Total cell delay = 2.336 ns ( 30.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.376 ns 69.71 % " "Info: Total interconnect delay = 5.376 ns ( 69.71 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "7.712 ns" { EN Q1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.712 ns" { EN EN~out0 Q1[0] } { 0.000ns 0.000ns 5.376ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.767 ns" { CLK Q1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 Q1[0] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "7.712 ns" { EN Q1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.712 ns" { EN EN~out0 Q1[0] } { 0.000ns 0.000ns 5.376ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 11 20:26:02 2006 " "Info: Processing ended: Tue Apr 11 20:26:02 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}