cnt8b.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 10 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 11 20:26:01 2006 " "Info: Processing started: Tue Apr 11 20:26:01 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off CNT8B -c CNT8B --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CNT8B -c CNT8B --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register Q1\[1\] Q1\[7\] 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"Q1\[1\]\" and destination register \"Q1\[7\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.269 ns + Longest register register " "Info: + Longest register to register delay is 2.269 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q1\[1\] 1 REG LC_X2_Y13_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y13_N1; Fanout = 5; REG Node = 'Q1\[1\]'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { Q1[1] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.532 ns) + CELL(0.564 ns) 1.096 ns Q1\[1\]~125 2 COMB LC_X2_Y13_N1 2 " "Info: 2: + IC(0.532 ns) + CELL(0.564 ns) = 1.096 ns; Loc. = LC_X2_Y13_N1; Fanout = 2; COMB Node = 'Q1\[1\]~125'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "1.096 ns" { Q1[1] Q1[1]~125 } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.174 ns Q1\[2\]~129 3 COMB LC_X2_Y13_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.174 ns; Loc. = LC_X2_Y13_N2; Fanout = 2; COMB Node = 'Q1\[2\]~129'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "0.078 ns" { Q1[1]~125 Q1[2]~129 } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.252 ns Q1\[3\]~133 4 COMB LC_X2_Y13_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.252 ns; Loc. = LC_X2_Y13_N3; Fanout = 2; COMB Node = 'Q1\[3\]~133'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "0.078 ns" { Q1[2]~129 Q1[3]~133 } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.430 ns Q1\[4\]~137 5 COMB LC_X2_Y13_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.430 ns; Loc. = LC_X2_Y13_N4; Fanout = 3; COMB Node = 'Q1\[4\]~137'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "0.178 ns" { Q1[3]~133 Q1[4]~137 } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.269 ns Q1\[7\] 6 REG LC_X2_Y13_N7 3 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.269 ns; Loc. = LC_X2_Y13_N7; Fanout = 3; REG Node = 'Q1\[7\]'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "0.839 ns" { Q1[4]~137 Q1[7] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.737 ns 76.55 % " "Info: Total cell delay = 1.737 ns ( 76.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.532 ns 23.45 % " "Info: Total interconnect delay = 0.532 ns ( 23.45 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.269 ns" { Q1[1] Q1[1]~125 Q1[2]~129 Q1[3]~133 Q1[4]~137 Q1[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.269 ns" { Q1[1] Q1[1]~125 Q1[2]~129 Q1[3]~133 Q1[4]~137 Q1[7] } { 0.000ns 0.532ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.767 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns Q1\[7\] 2 REG LC_X2_Y13_N7 3 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X2_Y13_N7; Fanout = 3; REG Node = 'Q1\[7\]'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "1.298 ns" { CLK Q1[7] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 78.79 % " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns 21.21 % " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.767 ns" { CLK Q1[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 Q1[7] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.767 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns Q1\[1\] 2 REG LC_X2_Y13_N1 5 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X2_Y13_N1; Fanout = 5; REG Node = 'Q1\[1\]'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "1.298 ns" { CLK Q1[1] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 78.79 % " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns 21.21 % " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.767 ns" { CLK Q1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 Q1[1] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.767 ns" { CLK Q1[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 Q1[7] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.767 ns" { CLK Q1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 Q1[1] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.269 ns" { Q1[1] Q1[1]~125 Q1[2]~129 Q1[3]~133 Q1[4]~137 Q1[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.269 ns" { Q1[1] Q1[1]~125 Q1[2]~129 Q1[3]~133 Q1[4]~137 Q1[7] } { 0.000ns 0.532ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.767 ns" { CLK Q1[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 Q1[7] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.767 ns" { CLK Q1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 Q1[1] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { Q1[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { Q1[7] } {  } {  } } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0}