cnt8b.fit.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 38 行 · 第 1/2 页

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "10 unused 3.30 1 9 0 " "Info: Number of I/O pins in group: 10 (unused VREF, 3.30 VCCIO, 1 input, 9 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 19 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  19 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 26 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.442 ns register register " "Info: Estimated most critical path is register to register delay of 2.442 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q1\[0\] 1 REG LAB_X2_Y13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y13; Fanout = 5; REG Node = 'Q1\[0\]'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { Q1[0] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.471 ns) + CELL(0.575 ns) 1.046 ns Q1\[0\]~121COUT1_153 2 COMB LAB_X2_Y13 2 " "Info: 2: + IC(0.471 ns) + CELL(0.575 ns) = 1.046 ns; Loc. = LAB_X2_Y13; Fanout = 2; COMB Node = 'Q1\[0\]~121COUT1_153'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "1.046 ns" { Q1[0] Q1[0]~121COUT1_153 } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.126 ns Q1\[1\]~125COUT1_154 3 COMB LAB_X2_Y13 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.126 ns; Loc. = LAB_X2_Y13; Fanout = 2; COMB Node = 'Q1\[1\]~125COUT1_154'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "0.080 ns" { Q1[0]~121COUT1_153 Q1[1]~125COUT1_154 } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.206 ns Q1\[2\]~129COUT1_155 4 COMB LAB_X2_Y13 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.206 ns; Loc. = LAB_X2_Y13; Fanout = 2; COMB Node = 'Q1\[2\]~129COUT1_155'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "0.080 ns" { Q1[1]~125COUT1_154 Q1[2]~129COUT1_155 } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.286 ns Q1\[3\]~133COUT1 5 COMB LAB_X2_Y13 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.286 ns; Loc. = LAB_X2_Y13; Fanout = 2; COMB Node = 'Q1\[3\]~133COUT1'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "0.080 ns" { Q1[2]~129COUT1_155 Q1[3]~133COUT1 } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.544 ns Q1\[4\]~137 6 COMB LAB_X2_Y13 3 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.544 ns; Loc. = LAB_X2_Y13; Fanout = 3; COMB Node = 'Q1\[4\]~137'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "0.258 ns" { Q1[3]~133COUT1 Q1[4]~137 } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 2.442 ns Q1\[5\] 7 REG LAB_X2_Y13 5 " "Info: 7: + IC(0.000 ns) + CELL(0.898 ns) = 2.442 ns; Loc. = LAB_X2_Y13; Fanout = 5; REG Node = 'Q1\[5\]'" {  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "0.898 ns" { Q1[4]~137 Q1[5] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.971 ns 80.71 % " "Info: Total cell delay = 1.971 ns ( 80.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.471 ns 19.29 % " "Info: Total interconnect delay = 0.471 ns ( 19.29 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "2.442 ns" { Q1[0] Q1[0]~121COUT1_153 Q1[1]~125COUT1_154 Q1[2]~129COUT1_155 Q1[3]~133COUT1 Q1[4]~137 Q1[5] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 11 20:25:53 2006 " "Info: Processing ended: Tue Apr 11 20:25:53 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}