cnt8b.fit.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 38 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 11 20:25:46 2006 " "Info: Processing started: Tue Apr 11 20:25:46 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off CNT8B -c CNT8B " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off CNT8B -c CNT8B" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "CNT8B EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design \"CNT8B\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "11 11 " "Info: No exact pin location assignment(s) for 11 pins of 11 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[0\] " "Info: Pin Q\[0\] not assigned to an exact location on the device" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Q\[0\]" } } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { Q[0] } "NODE_NAME" } "" } } { "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" "" { Q[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[1\] " "Info: Pin Q\[1\] not assigned to an exact location on the device" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Q\[1\]" } } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { Q[1] } "NODE_NAME" } "" } } { "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" "" { Q[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[2\] " "Info: Pin Q\[2\] not assigned to an exact location on the device" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Q\[2\]" } } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { Q[2] } "NODE_NAME" } "" } } { "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" "" { Q[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[3\] " "Info: Pin Q\[3\] not assigned to an exact location on the device" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Q\[3\]" } } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { Q[3] } "NODE_NAME" } "" } } { "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" "" { Q[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[4\] " "Info: Pin Q\[4\] not assigned to an exact location on the device" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Q\[4\]" } } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { Q[4] } "NODE_NAME" } "" } } { "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" "" { Q[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[5\] " "Info: Pin Q\[5\] not assigned to an exact location on the device" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Q\[5\]" } } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { Q[5] } "NODE_NAME" } "" } } { "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" "" { Q[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[6\] " "Info: Pin Q\[6\] not assigned to an exact location on the device" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Q\[6\]" } } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { Q[6] } "NODE_NAME" } "" } } { "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" "" { Q[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q\[7\] " "Info: Pin Q\[7\] not assigned to an exact location on the device" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Q\[7\]" } } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { Q[7] } "NODE_NAME" } "" } } { "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" "" { Q[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "C " "Info: Pin C not assigned to an exact location on the device" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 8 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "C" } } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { C } "NODE_NAME" } "" } } { "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" "" { C } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLK " "Info: Pin CLK not assigned to an exact location on the device" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { CLK } "NODE_NAME" } "" } } { "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" "" { CLK } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "EN " "Info: Pin EN not assigned to an exact location on the device" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "EN" } } } } { "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/" "" "" { EN } "NODE_NAME" } "" } } { "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" { Floorplan "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.fld" "" "" { EN } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in PIN 17 " "Info: Automatically promoted signal \"CLK\" to use Global clock in PIN 17" {  } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/1c3t/INIT_DATA/CNT8B.vhd" 6 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}