singt.fit.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 47 行 · 第 1/2 页

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.401 ns register register " "Info: Estimated most critical path is register to register delay of 4.401 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] 1 REG LAB_X10_Y5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y5; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(0.442 ns) 1.506 ns sld_hub:sld_hub_inst\|hub_tdo~359 2 COMB LAB_X10_Y6 1 " "Info: 2: + IC(1.064 ns) + CELL(0.442 ns) = 1.506 ns; Loc. = LAB_X10_Y6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~359'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "1.506 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.912 ns) + CELL(0.442 ns) 2.860 ns sld_hub:sld_hub_inst\|hub_tdo~360 3 COMB LAB_X12_Y6 1 " "Info: 3: + IC(0.912 ns) + CELL(0.442 ns) = 2.860 ns; Loc. = LAB_X12_Y6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~360'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "1.354 ns" { sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.232 ns) + CELL(0.309 ns) 4.401 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LAB_X16_Y6 0 " "Info: 4: + IC(1.232 ns) + CELL(0.309 ns) = 4.401 ns; Loc. = LAB_X16_Y6; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "1.541 ns" { sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.193 ns 27.11 % " "Info: Total cell delay = 1.193 ns ( 27.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.208 ns 72.89 % " "Info: Total interconnect delay = 3.208 ns ( 72.89 % )" {  } {  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "4.401 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 1 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 1%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] -- routed using non-global resources" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/EDA/DDS/cosx/SINGT.fld" "" { Floorplan "E:/EDA/DDS/cosx/SINGT.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\] -- routed using non-global resources" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/EDA/DDS/cosx/SINGT.fld" "" { Floorplan "E:/EDA/DDS/cosx/SINGT.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\] -- routed using non-global resources" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/EDA/DDS/cosx/SINGT.fld" "" { Floorplan "E:/EDA/DDS/cosx/SINGT.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\] -- routed using non-global resources" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/EDA/DDS/cosx/SINGT.fld" "" { Floorplan "E:/EDA/DDS/cosx/SINGT.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\] -- routed using non-global resources" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/EDA/DDS/cosx/SINGT.fld" "" { Floorplan "E:/EDA/DDS/cosx/SINGT.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\] -- routed using non-global resources" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/EDA/DDS/cosx/SINGT.fld" "" { Floorplan "E:/EDA/DDS/cosx/SINGT.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] } "NODE_NAME" } }  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/EDA/DDS/cosx/SINGT.fld" "" { Floorplan "E:/EDA/DDS/cosx/SINGT.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 09 19:55:04 2006 " "Info: Processing ended: Sun Apr 09 19:55:04 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0}  } {  } 0}