singt3.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 8 行 · 第 1/2 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register q\[0\] register q\[2\] 257.6 MHz 3.882 ns Internal " "Info: Clock \"clk\" has Internal fmax of 257.6 MHz between source register \"q\[0\]\" and destination register \"q\[2\]\" (period= 3.882 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.621 ns + Longest register register " "Info: + Longest register to register delay is 3.621 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[0\] 1 REG LC_X5_Y2_N1 44 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N1; Fanout = 44; REG Node = 'q\[0\]'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "" { q[0] } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/1c3t/cosx/singt3.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.557 ns) + CELL(0.590 ns) 1.147 ns Mux~2537 2 COMB LC_X5_Y2_N8 3 " "Info: 2: + IC(0.557 ns) + CELL(0.590 ns) = 1.147 ns; Loc. = LC_X5_Y2_N8; Fanout = 3; COMB Node = 'Mux~2537'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "1.147 ns" { q[0] Mux~2537 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.442 ns) 2.024 ns LessThan~75 3 COMB LC_X5_Y2_N0 7 " "Info: 3: + IC(0.435 ns) + CELL(0.442 ns) = 2.024 ns; Loc. = LC_X5_Y2_N0; Fanout = 7; COMB Node = 'LessThan~75'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "0.877 ns" { Mux~2537 LessThan~75 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.485 ns) + CELL(1.112 ns) 3.621 ns q\[2\] 4 REG LC_X5_Y2_N3 41 " "Info: 4: + IC(0.485 ns) + CELL(1.112 ns) = 3.621 ns; Loc. = LC_X5_Y2_N3; Fanout = 41; REG Node = 'q\[2\]'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "1.597 ns" { LessThan~75 q[2] } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/1c3t/cosx/singt3.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.144 ns 59.21 % " "Info: Total cell delay = 2.144 ns ( 59.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.477 ns 40.79 % " "Info: Total interconnect delay = 1.477 ns ( 40.79 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "3.621 ns" { q[0] Mux~2537 LessThan~75 q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.621 ns" { q[0] Mux~2537 LessThan~75 q[2] } { 0.000ns 0.557ns 0.435ns 0.485ns } { 0.000ns 0.590ns 0.442ns 1.112ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 7; CLK Node = 'clk'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "" { clk } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/1c3t/cosx/singt3.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns q\[2\] 2 REG LC_X5_Y2_N3 41 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X5_Y2_N3; Fanout = 41; REG Node = 'q\[2\]'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "1.261 ns" { clk q[2] } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/1c3t/cosx/singt3.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "2.730 ns" { clk q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 q[2] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.730 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 7; CLK Node = 'clk'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "" { clk } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/1c3t/cosx/singt3.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns q\[0\] 2 REG LC_X5_Y2_N1 44 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X5_Y2_N1; Fanout = 44; REG Node = 'q\[0\]'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "1.261 ns" { clk q[0] } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/1c3t/cosx/singt3.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "2.730 ns" { clk q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 q[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "2.730 ns" { clk q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 q[2] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "2.730 ns" { clk q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 q[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "singt3.vhd" "" { Text "E:/EDA/DDS/1c3t/cosx/singt3.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "singt3.vhd" "" { Text "E:/EDA/DDS/1c3t/cosx/singt3.vhd" 12 -1 0 } }  } 0}  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "3.621 ns" { q[0] Mux~2537 LessThan~75 q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.621 ns" { q[0] Mux~2537 LessThan~75 q[2] } { 0.000ns 0.557ns 0.435ns 0.485ns } { 0.000ns 0.590ns 0.442ns 1.112ns } } } { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "2.730 ns" { clk q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 q[2] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "2.730 ns" { clk q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 q[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[5\] q\[0\] 12.916 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[5\]\" through register \"q\[0\]\" is 12.916 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.730 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 7; CLK Node = 'clk'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "" { clk } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/1c3t/cosx/singt3.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns q\[0\] 2 REG LC_X5_Y2_N1 44 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X5_Y2_N1; Fanout = 44; REG Node = 'q\[0\]'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "1.261 ns" { clk q[0] } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/1c3t/cosx/singt3.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "2.730 ns" { clk q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 q[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "singt3.vhd" "" { Text "E:/EDA/DDS/1c3t/cosx/singt3.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.962 ns + Longest register pin " "Info: + Longest register to pin delay is 9.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[0\] 1 REG LC_X5_Y2_N1 44 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N1; Fanout = 44; REG Node = 'q\[0\]'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "" { q[0] } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/1c3t/cosx/singt3.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.435 ns) + CELL(0.590 ns) 2.025 ns Mux~2536 2 COMB LC_X5_Y1_N9 1 " "Info: 2: + IC(1.435 ns) + CELL(0.590 ns) = 2.025 ns; Loc. = LC_X5_Y1_N9; Fanout = 1; COMB Node = 'Mux~2536'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "2.025 ns" { q[0] Mux~2536 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.221 ns) + CELL(0.442 ns) 3.688 ns Mux~2538 3 COMB LC_X5_Y2_N9 1 " "Info: 3: + IC(1.221 ns) + CELL(0.442 ns) = 3.688 ns; Loc. = LC_X5_Y2_N9; Fanout = 1; COMB Node = 'Mux~2538'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "1.663 ns" { Mux~2536 Mux~2538 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(0.590 ns) 5.378 ns Mux~2540 4 COMB LC_X4_Y2_N6 1 " "Info: 4: + IC(1.100 ns) + CELL(0.590 ns) = 5.378 ns; Loc. = LC_X4_Y2_N6; Fanout = 1; COMB Node = 'Mux~2540'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "1.690 ns" { Mux~2538 Mux~2540 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.590 ns) 6.423 ns Mux~2544 5 COMB LC_X4_Y2_N4 1 " "Info: 5: + IC(0.455 ns) + CELL(0.590 ns) = 6.423 ns; Loc. = LC_X4_Y2_N4; Fanout = 1; COMB Node = 'Mux~2544'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "1.045 ns" { Mux~2540 Mux~2544 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.415 ns) + CELL(2.124 ns) 9.962 ns dout\[5\] 6 PIN PIN_33 0 " "Info: 6: + IC(1.415 ns) + CELL(2.124 ns) = 9.962 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'dout\[5\]'" {  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "3.539 ns" { Mux~2544 dout[5] } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/1c3t/cosx/singt3.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.336 ns 43.53 % " "Info: Total cell delay = 4.336 ns ( 43.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.626 ns 56.47 % " "Info: Total interconnect delay = 5.626 ns ( 56.47 % )" {  } {  } 0}  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "9.962 ns" { q[0] Mux~2536 Mux~2538 Mux~2540 Mux~2544 dout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.962 ns" { q[0] Mux~2536 Mux~2538 Mux~2540 Mux~2544 dout[5] } { 0.000ns 1.435ns 1.221ns 1.100ns 0.455ns 1.415ns } { 0.000ns 0.590ns 0.442ns 0.590ns 0.590ns 2.124ns } } }  } 0}  } { { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "2.730 ns" { clk q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 q[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/1c3t/cosx/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/1c3t/cosx/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/1c3t/cosx/" "" "9.962 ns" { q[0] Mux~2536 Mux~2538 Mux~2540 Mux~2544 dout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.962 ns" { q[0] Mux~2536 Mux~2538 Mux~2540 Mux~2544 dout[5] } { 0.000ns 1.435ns 1.221ns 1.100ns 0.455ns 1.415ns } { 0.000ns 0.590ns 0.442ns 0.590ns 0.590ns 2.124ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 19:22:08 2006 " "Info: Processing ended: Fri Apr 14 19:22:08 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}