data_rom.map.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 22 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 09 16:49:33 2006 " "Info: Processing started: Sun Apr 09 16:49:33 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off data_rom -c data_rom " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off data_rom -c data_rom" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_rom.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file data_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 data_rom-SYN " "Info: Found design unit 1: data_rom-SYN" {  } { { "data_rom.vhd" "" { Text "D:/DDS/cosx/data_rom.vhd" 55 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 data_rom " "Info: Found entity 1: data_rom" {  } { { "data_rom.vhd" "" { Text "D:/DDS/cosx/data_rom.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/altsyncram.tdf" 431 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_kds.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_kds.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_kds " "Info: Found entity 1: altsyncram_kds" {  } { { "db/altsyncram_kds.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_kds.tdf" 33 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_s5a2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_s5a2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_s5a2 " "Info: Found entity 1: altsyncram_s5a2" {  } { { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 40 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/sld_mod_ram_rom.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/sld_mod_ram_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mod_ram_rom_pack " "Info: Found design unit 1: sld_mod_ram_rom_pack" {  } { { "sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_mod_ram_rom.vhd" 4 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_mod_ram_rom-rtl " "Info: Found design unit 2: sld_mod_ram_rom-rtl" {  } { { "sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_mod_ram_rom.vhd" 72 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mod_ram_rom " "Info: Found entity 1: sld_mod_ram_rom" {  } { { "sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_mod_ram_rom.vhd" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd" 1012 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd" 997 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 43 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/lpm_decode.tdf" 68 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_9ie.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_9ie " "Info: Found entity 1: decode_9ie" {  } { { "db/decode_9ie.tdf" "" { Text "D:/DDS/cosx/db/decode_9ie.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~49 7 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=7) from the following logic: \"altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~49\"" {  } { { "sld_mod_ram_rom.vhd" "ram_rom_addr_reg\[0\]~49" { Text "c:/altera/quartus42/libraries/megafunctions/sld_mod_ram_rom.vhd" 394 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_shift_cntr_reg\[0\]~12 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_shift_cntr_reg\[0\]~12\"" {  } { { "sld_mod_ram_rom.vhd" "ram_rom_data_shift_cntr_reg\[0\]~12" { Text "c:/altera/quartus42/libraries/megafunctions/sld_mod_ram_rom.vhd" 511 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_lu8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_lu8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_lu8 " "Info: Found entity 1: cntr_lu8" {  } { { "db/cntr_lu8.tdf" "" { Text "D:/DDS/cosx/db/cntr_lu8.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_pd8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_pd8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_pd8 " "Info: Found entity 1: cntr_pd8" {  } { { "db/cntr_pd8.tdf" "" { Text "D:/DDS/cosx/db/cntr_pd8.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "198 " "Info: Implemented 198 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "169 " "Info: Implemented 169 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 09 16:50:01 2006 " "Info: Processing ended: Sun Apr 09 16:50:01 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Info: Elapsed time: 00:00:30" {  } {  } 0}  } {  } 0}