data_rom.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 12 行 · 第 1/4 页

{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[9\] altera_internal_jtag altera_internal_jtag~TCKUTAP 3.670 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[9\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 3.670 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.271 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 127 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 127; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.560 ns) + CELL(0.711 ns) 5.271 ns sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[9\] 2 REG LC_X8_Y9_N4 2 " "Info: 2: + IC(4.560 ns) + CELL(0.711 ns) = 5.271 ns; Loc. = LC_X8_Y9_N4; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[9\]'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "5.271 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.49 % " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.560 ns 86.51 % " "Info: Total interconnect delay = 4.560 ns ( 86.51 % )" {  } {  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "5.271 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.271 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] } { 0.000ns 4.560ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.616 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.616 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y6_N1 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 10; PIN Node = 'altera_internal_jtag'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "" { altera_internal_jtag } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.501 ns) + CELL(0.115 ns) 1.616 ns sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[9\] 2 REG LC_X8_Y9_N4 2 " "Info: 2: + IC(1.501 ns) + CELL(0.115 ns) = 1.616 ns; Loc. = LC_X8_Y9_N4; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[9\]'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "1.616 ns" { altera_internal_jtag sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 7.12 % " "Info: Total cell delay = 0.115 ns ( 7.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.501 ns 92.88 % " "Info: Total interconnect delay = 1.501 ns ( 92.88 % )" {  } {  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "1.616 ns" { altera_internal_jtag sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.616 ns" { altera_internal_jtag sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] } { 0.000ns 1.501ns } { 0.000ns 0.115ns } } }  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "5.271 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.271 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] } { 0.000ns 4.560ns } { 0.000ns 0.711ns } } } { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "1.616 ns" { altera_internal_jtag sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.616 ns" { altera_internal_jtag sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] } { 0.000ns 1.501ns } { 0.000ns 0.115ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 09 16:50:43 2006 " "Info: Processing ended: Sun Apr 09 16:50:43 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}