data_rom.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 12 行 · 第 1/4 页

{ "Info" "ITDB_TSU_RESULT" "altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_address_reg1 address\[1\] inclock 5.267 ns memory " "Info: tsu for memory \"altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_address_reg1\" (data pin = \"address\[1\]\", clock pin = \"inclock\") is 5.267 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.966 ns + Longest pin memory " "Info: + Longest pin to memory delay is 7.966 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns address\[1\] 1 PIN PIN_128 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_128; Fanout = 1; PIN Node = 'address\[1\]'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "" { address[1] } "NODE_NAME" } "" } } { "data_rom.vhd" "" { Text "D:/DDS/cosx/data_rom.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.108 ns) + CELL(0.383 ns) 7.966 ns altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_address_reg1 2 MEM M4K_X13_Y9 8 " "Info: 2: + IC(6.108 ns) + CELL(0.383 ns) = 7.966 ns; Loc. = M4K_X13_Y9; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_address_reg1'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "6.491 ns" { address[1] altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg1 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 276 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.858 ns 23.32 % " "Info: Total cell delay = 1.858 ns ( 23.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.108 ns 76.68 % " "Info: Total interconnect delay = 6.108 ns ( 76.68 % )" {  } {  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "7.966 ns" { address[1] altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "7.966 ns" { address[1] address[1]~out0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg1 } { 0.000ns 0.000ns 6.108ns } { 0.000ns 1.475ns 0.383ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 276 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock destination 2.792 ns - Shortest memory " "Info: - Shortest clock path from clock \"inclock\" to destination memory is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns inclock 1 CLK PIN_17 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 24; CLK Node = 'inclock'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "" { inclock } "NODE_NAME" } "" } } { "data_rom.vhd" "" { Text "D:/DDS/cosx/data_rom.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.722 ns) 2.792 ns altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_address_reg1 2 MEM M4K_X13_Y9 8 " "Info: 2: + IC(0.601 ns) + CELL(0.722 ns) = 2.792 ns; Loc. = M4K_X13_Y9; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_address_reg1'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "1.323 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg1 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 276 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 78.47 % " "Info: Total cell delay = 2.191 ns ( 78.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.53 % " "Info: Total interconnect delay = 0.601 ns ( 21.53 % )" {  } {  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "2.792 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.792 ns" { inclock inclock~out0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg1 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } }  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "7.966 ns" { address[1] altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "7.966 ns" { address[1] address[1]~out0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg1 } { 0.000ns 0.000ns 6.108ns } { 0.000ns 1.475ns 0.383ns } } } { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "2.792 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.792 ns" { inclock inclock~out0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg1 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "inclock q\[2\] altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_address_reg0 12.711 ns memory " "Info: tco from clock \"inclock\" to destination pin \"q\[2\]\" through memory \"altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_address_reg0\" is 12.711 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock source 2.792 ns + Longest memory " "Info: + Longest clock path from clock \"inclock\" to source memory is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns inclock 1 CLK PIN_17 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 24; CLK Node = 'inclock'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "" { inclock } "NODE_NAME" } "" } } { "data_rom.vhd" "" { Text "D:/DDS/cosx/data_rom.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.722 ns) 2.792 ns altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_address_reg0 2 MEM M4K_X13_Y9 8 " "Info: 2: + IC(0.601 ns) + CELL(0.722 ns) = 2.792 ns; Loc. = M4K_X13_Y9; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_address_reg0'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "1.323 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 276 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 78.47 % " "Info: Total cell delay = 2.191 ns ( 78.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.53 % " "Info: Total interconnect delay = 0.601 ns ( 21.53 % )" {  } {  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "2.792 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.792 ns" { inclock inclock~out0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 276 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.269 ns + Longest memory pin " "Info: + Longest memory to pin delay is 9.269 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_address_reg0 1 MEM M4K_X13_Y9 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y9; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_address_reg0'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "" { altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 276 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|q_a\[2\] 2 MEM M4K_X13_Y9 1 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y9; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|q_a\[2\]'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "4.308 ns" { altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|q_a[2] } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 47 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.853 ns) + CELL(2.108 ns) 9.269 ns q\[2\] 3 PIN PIN_52 0 " "Info: 3: + IC(2.853 ns) + CELL(2.108 ns) = 9.269 ns; Loc. = PIN_52; Fanout = 0; PIN Node = 'q\[2\]'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "4.961 ns" { altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|q_a[2] q[2] } "NODE_NAME" } "" } } { "data_rom.vhd" "" { Text "D:/DDS/cosx/data_rom.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.416 ns 69.22 % " "Info: Total cell delay = 6.416 ns ( 69.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.853 ns 30.78 % " "Info: Total interconnect delay = 2.853 ns ( 30.78 % )" {  } {  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "9.269 ns" { altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|q_a[2] q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "9.269 ns" { altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|q_a[2] q[2] } { 0.000ns 0.000ns 2.853ns } { 0.000ns 4.308ns 2.108ns } } }  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "2.792 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.792 ns" { inclock inclock~out0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } } { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "9.269 ns" { altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|q_a[2] q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "9.269 ns" { altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|q_a[2] q[2] } { 0.000ns 0.000ns 2.853ns } { 0.000ns 4.308ns 2.108ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y6_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_90 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_90; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 100.00 % " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.124ns } } }  } 0}