data_rom.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 12 行 · 第 1/4 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "inclock " "Info: Assuming node \"inclock\" is an undefined clock" {  } { { "data_rom.vhd" "" { Text "D:/DDS/cosx/data_rom.vhd" 49 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "inclock" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "inclock memory altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_datain_reg7 memory altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_memory_reg7 197.01 MHz 5.076 ns Internal " "Info: Clock \"inclock\" has Internal fmax of 197.01 MHz between source memory \"altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_datain_reg7\" and destination memory \"altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_memory_reg7\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_datain_reg7 1 MEM M4K_X13_Y9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y9; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_datain_reg7'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "" { altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 276 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_memory_reg7 2 MEM M4K_X13_Y9 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y9; Fanout = 0; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_memory_reg7'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "4.319 ns" { altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_datain_reg7 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 276 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns 100.00 % " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "4.319 ns" { altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_datain_reg7 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "4.319 ns" { altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_datain_reg7 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock destination 2.778 ns + Shortest memory " "Info: + Shortest clock path from clock \"inclock\" to destination memory is 2.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns inclock 1 CLK PIN_17 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 24; CLK Node = 'inclock'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "" { inclock } "NODE_NAME" } "" } } { "data_rom.vhd" "" { Text "D:/DDS/cosx/data_rom.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.708 ns) 2.778 ns altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_memory_reg7 2 MEM M4K_X13_Y9 0 " "Info: 2: + IC(0.601 ns) + CELL(0.708 ns) = 2.778 ns; Loc. = M4K_X13_Y9; Fanout = 0; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_memory_reg7'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "1.309 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 276 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns 78.37 % " "Info: Total cell delay = 2.177 ns ( 78.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.63 % " "Info: Total interconnect delay = 0.601 ns ( 21.63 % )" {  } {  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "2.778 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.778 ns" { inclock inclock~out0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_memory_reg7 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.708ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock source 2.792 ns - Longest memory " "Info: - Longest clock path from clock \"inclock\" to source memory is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns inclock 1 CLK PIN_17 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 24; CLK Node = 'inclock'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "" { inclock } "NODE_NAME" } "" } } { "data_rom.vhd" "" { Text "D:/DDS/cosx/data_rom.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.722 ns) 2.792 ns altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_datain_reg7 2 MEM M4K_X13_Y9 1 " "Info: 2: + IC(0.601 ns) + CELL(0.722 ns) = 2.792 ns; Loc. = M4K_X13_Y9; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a7~porta_datain_reg7'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "1.323 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 276 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 78.47 % " "Info: Total cell delay = 2.191 ns ( 78.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.53 % " "Info: Total interconnect delay = 0.601 ns ( 21.53 % )" {  } {  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "2.792 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.792 ns" { inclock inclock~out0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_datain_reg7 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } }  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "2.778 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.778 ns" { inclock inclock~out0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_memory_reg7 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.708ns } } } { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "2.792 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.792 ns" { inclock inclock~out0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_datain_reg7 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 276 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_s5a2.tdf" "" { Text "D:/DDS/cosx/db/altsyncram_s5a2.tdf" 276 2 0 } }  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "4.319 ns" { altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_datain_reg7 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "4.319 ns" { altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_datain_reg7 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "2.778 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.778 ns" { inclock inclock~out0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_memory_reg7 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.708ns } } } { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "2.792 ns" { inclock altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.792 ns" { inclock inclock~out0 altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a7~porta_datain_reg7 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] register sld_hub:sld_hub_inst\|HUB_TDO~reg0 115.82 MHz 8.634 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 115.82 MHz between source register \"sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]\" and destination register \"sld_hub:sld_hub_inst\|HUB_TDO~reg0\" (period= 8.634 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.028 ns + Longest register register " "Info: + Longest register to register delay is 4.028 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 1 REG LC_X11_Y10_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y10_N8; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.590 ns) + CELL(0.590 ns) 2.180 ns sld_hub:sld_hub_inst\|HUB_TDO~350 2 COMB LC_X9_Y9_N4 1 " "Info: 2: + IC(1.590 ns) + CELL(0.590 ns) = 2.180 ns; Loc. = LC_X9_Y9_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~350'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "2.180 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|HUB_TDO~350 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.241 ns) + CELL(0.607 ns) 4.028 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 3 REG LC_X10_Y7_N0 0 " "Info: 3: + IC(1.241 ns) + CELL(0.607 ns) = 4.028 ns; Loc. = LC_X10_Y7_N0; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "1.848 ns" { sld_hub:sld_hub_inst|HUB_TDO~350 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.197 ns 29.72 % " "Info: Total cell delay = 1.197 ns ( 29.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.831 ns 70.28 % " "Info: Total interconnect delay = 2.831 ns ( 70.28 % )" {  } {  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "4.028 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|HUB_TDO~350 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "4.028 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|HUB_TDO~350 sld_hub:sld_hub_inst|HUB_TDO~reg0 } { 0.000ns 1.590ns 1.241ns } { 0.000ns 0.590ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.028 ns - Smallest " "Info: - Smallest clock skew is -0.028 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.243 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.243 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 127 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 127; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.532 ns) + CELL(0.711 ns) 5.243 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 2 REG LC_X10_Y7_N0 0 " "Info: 2: + IC(4.532 ns) + CELL(0.711 ns) = 5.243 ns; Loc. = LC_X10_Y7_N0; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "5.243 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.56 % " "Info: Total cell delay = 0.711 ns ( 13.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.532 ns 86.44 % " "Info: Total interconnect delay = 4.532 ns ( 86.44 % )" {  } {  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "5.243 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.243 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } { 0.000ns 4.532ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.271 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 127 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 127; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.560 ns) + CELL(0.711 ns) 5.271 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 2 REG LC_X11_Y10_N8 1 " "Info: 2: + IC(4.560 ns) + CELL(0.711 ns) = 5.271 ns; Loc. = LC_X11_Y10_N8; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "5.271 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.49 % " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.560 ns 86.51 % " "Info: Total interconnect delay = 4.560 ns ( 86.51 % )" {  } {  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "5.271 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.271 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.560ns } { 0.000ns 0.711ns } } }  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "5.243 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.243 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } { 0.000ns 4.532ns } { 0.000ns 0.711ns } } } { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "5.271 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.271 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.560ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } } { "sld_hub.vhd" "" { Text "c:/altera/quartus42/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0}  } { { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "4.028 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|HUB_TDO~350 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "4.028 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|HUB_TDO~350 sld_hub:sld_hub_inst|HUB_TDO~reg0 } { 0.000ns 1.590ns 1.241ns } { 0.000ns 0.590ns 0.607ns } } } { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "5.243 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.243 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } { 0.000ns 4.532ns } { 0.000ns 0.711ns } } } { "D:/DDS/cosx/db/data_rom_cmp.qrpt" "" { Report "D:/DDS/cosx/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "D:/DDS/cosx/db/data_rom.quartus_db" { Floorplan "D:/DDS/cosx/" "" "5.271 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.271 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.560ns } { 0.000ns 0.711ns } } }  } 0}