singt.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 12 行 · 第 1/4 页

{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\] altera_internal_jtag altera_internal_jtag~TCKUTAP -1.257 ns register " "Info: tsu for register \"sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is -1.257 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.978 ns + Longest pin register " "Info: + Longest pin to register delay is 3.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y6_N1 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 10; PIN Node = 'altera_internal_jtag'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { altera_internal_jtag } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.962 ns) + CELL(0.292 ns) 2.254 ns sld_hub:sld_hub_inst\|HUB_BYPASS_REG~18 2 COMB LC_X15_Y5_N7 2 " "Info: 2: + IC(1.962 ns) + CELL(0.292 ns) = 2.254 ns; Loc. = LC_X15_Y5_N7; Fanout = 2; COMB Node = 'sld_hub:sld_hub_inst\|HUB_BYPASS_REG~18'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "2.254 ns" { altera_internal_jtag sld_hub:sld_hub_inst|HUB_BYPASS_REG~18 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 315 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.609 ns) + CELL(0.115 ns) 3.978 ns sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\] 3 REG LC_X17_Y6_N3 2 " "Info: 3: + IC(1.609 ns) + CELL(0.115 ns) = 3.978 ns; Loc. = LC_X17_Y6_N3; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\]'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "1.724 ns" { sld_hub:sld_hub_inst|HUB_BYPASS_REG~18 sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns 10.23 % " "Info: Total cell delay = 0.407 ns ( 10.23 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.571 ns 89.77 % " "Info: Total interconnect delay = 3.571 ns ( 89.77 % )" {  } {  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "3.978 ns" { altera_internal_jtag sld_hub:sld_hub_inst|HUB_BYPASS_REG~18 sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.978 ns" { altera_internal_jtag sld_hub:sld_hub_inst|HUB_BYPASS_REG~18 sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } { 0.000ns 1.962ns 1.609ns } { 0.000ns 0.292ns 0.115ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.272 ns - Shortest register " "Info: - Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 127 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 127; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\] 2 REG LC_X17_Y6_N3 2 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X17_Y6_N3; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\]'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.49 % " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns 86.51 % " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "3.978 ns" { altera_internal_jtag sld_hub:sld_hub_inst|HUB_BYPASS_REG~18 sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.978 ns" { altera_internal_jtag sld_hub:sld_hub_inst|HUB_BYPASS_REG~18 sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } { 0.000ns 1.962ns 1.609ns } { 0.000ns 0.292ns 0.115ns } } } { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DOUT\[5\] data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_address_reg0 17.343 ns memory " "Info: tco from clock \"CLK\" to destination pin \"DOUT\[5\]\" through memory \"data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_address_reg0\" is 17.343 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.496 ns + Longest memory " "Info: + Longest clock path from clock \"CLK\" to source memory is 7.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK 1 CLK PIN_123 31 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 31; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { CLK } "NODE_NAME" } "" } } { "SINGT.vhd" "" { Text "E:/EDA/DDS/cosx/SINGT.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.299 ns) + CELL(0.722 ns) 7.496 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_address_reg0 2 MEM M4K_X13_Y6 8 " "Info: 2: + IC(5.299 ns) + CELL(0.722 ns) = 7.496 ns; Loc. = M4K_X13_Y6; Fanout = 8; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_address_reg0'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "6.021 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "E:/EDA/DDS/cosx/db/altsyncram_s5a2.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.197 ns 29.31 % " "Info: Total cell delay = 2.197 ns ( 29.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.299 ns 70.69 % " "Info: Total interconnect delay = 5.299 ns ( 70.69 % )" {  } {  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "7.496 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.496 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_s5a2.tdf" "" { Text "E:/EDA/DDS/cosx/db/altsyncram_s5a2.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.197 ns + Longest memory pin " "Info: + Longest memory to pin delay is 9.197 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_address_reg0 1 MEM M4K_X13_Y6 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y6; Fanout = 8; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_address_reg0'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "E:/EDA/DDS/cosx/db/altsyncram_s5a2.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|q_a\[5\] 2 MEM M4K_X13_Y6 1 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y6; Fanout = 1; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|q_a\[5\]'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "4.308 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_address_reg0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|q_a[5] } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "E:/EDA/DDS/cosx/db/altsyncram_s5a2.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.781 ns) + CELL(2.108 ns) 9.197 ns DOUT\[5\] 3 PIN PIN_70 0 " "Info: 3: + IC(2.781 ns) + CELL(2.108 ns) = 9.197 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'DOUT\[5\]'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "4.889 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|q_a[5] DOUT[5] } "NODE_NAME" } "" } } { "SINGT.vhd" "" { Text "E:/EDA/DDS/cosx/SINGT.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.416 ns 69.76 % " "Info: Total cell delay = 6.416 ns ( 69.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.781 ns 30.24 % " "Info: Total interconnect delay = 2.781 ns ( 30.24 % )" {  } {  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "9.197 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_address_reg0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|q_a[5] DOUT[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.197 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_address_reg0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|q_a[5] DOUT[5] } { 0.000ns 0.000ns 2.781ns } { 0.000ns 4.308ns 2.108ns } } }  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "7.496 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.496 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.722ns } } } { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "9.197 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_address_reg0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|q_a[5] DOUT[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.197 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_address_reg0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|q_a[5] DOUT[5] } { 0.000ns 0.000ns 2.781ns } { 0.000ns 4.308ns 2.108ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y6_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_90 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_90; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 100.00 % " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.124ns } } }  } 0}