singt.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 12 行 · 第 1/4 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "SINGT.vhd" "" { Text "E:/EDA/DDS/cosx/SINGT.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK memory data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_datain_reg7 memory data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_memory_reg7 197.01 MHz 5.076 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 197.01 MHz between source memory \"data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_datain_reg7\" and destination memory \"data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_memory_reg7\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_datain_reg7 1 MEM M4K_X13_Y6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y6; Fanout = 1; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_datain_reg7'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "E:/EDA/DDS/cosx/db/altsyncram_s5a2.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_memory_reg7 2 MEM M4K_X13_Y6 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y6; Fanout = 0; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_memory_reg7'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "4.319 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_datain_reg7 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "E:/EDA/DDS/cosx/db/altsyncram_s5a2.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns 100.00 % " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "4.319 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_datain_reg7 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_datain_reg7 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.482 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 7.482 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK 1 CLK PIN_123 31 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 31; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { CLK } "NODE_NAME" } "" } } { "SINGT.vhd" "" { Text "E:/EDA/DDS/cosx/SINGT.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.299 ns) + CELL(0.708 ns) 7.482 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_memory_reg7 2 MEM M4K_X13_Y6 0 " "Info: 2: + IC(5.299 ns) + CELL(0.708 ns) = 7.482 ns; Loc. = M4K_X13_Y6; Fanout = 0; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_memory_reg7'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "6.007 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "E:/EDA/DDS/cosx/db/altsyncram_s5a2.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.183 ns 29.18 % " "Info: Total cell delay = 2.183 ns ( 29.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.299 ns 70.82 % " "Info: Total interconnect delay = 5.299 ns ( 70.82 % )" {  } {  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "7.482 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.482 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.708ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.496 ns - Longest memory " "Info: - Longest clock path from clock \"CLK\" to source memory is 7.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK 1 CLK PIN_123 31 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 31; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { CLK } "NODE_NAME" } "" } } { "SINGT.vhd" "" { Text "E:/EDA/DDS/cosx/SINGT.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.299 ns) + CELL(0.722 ns) 7.496 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_datain_reg7 2 MEM M4K_X13_Y6 1 " "Info: 2: + IC(5.299 ns) + CELL(0.722 ns) = 7.496 ns; Loc. = M4K_X13_Y6; Fanout = 1; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_kds:auto_generated\|altsyncram_s5a2:altsyncram1\|ram_block3a0~porta_datain_reg7'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "6.021 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_s5a2.tdf" "" { Text "E:/EDA/DDS/cosx/db/altsyncram_s5a2.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.197 ns 29.31 % " "Info: Total cell delay = 2.197 ns ( 29.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.299 ns 70.69 % " "Info: Total interconnect delay = 5.299 ns ( 70.69 % )" {  } {  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "7.496 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.496 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_datain_reg7 } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.722ns } } }  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "7.482 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.482 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.708ns } } } { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "7.496 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.496 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_datain_reg7 } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_s5a2.tdf" "" { Text "E:/EDA/DDS/cosx/db/altsyncram_s5a2.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_s5a2.tdf" "" { Text "E:/EDA/DDS/cosx/db/altsyncram_s5a2.tdf" 46 2 0 } }  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "4.319 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_datain_reg7 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_datain_reg7 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "7.482 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.482 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.708ns } } } { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "7.496 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.496 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_kds:auto_generated|altsyncram_s5a2:altsyncram1|ram_block3a0~porta_datain_reg7 } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.722ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] register sld_hub:sld_hub_inst\|hub_tdo 97.73 MHz 10.232 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 97.73 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 10.232 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.908 ns + Longest register register " "Info: + Longest register to register delay is 4.908 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] 1 REG LC_X10_Y5_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y5_N0; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.298 ns) + CELL(0.442 ns) 1.740 ns sld_hub:sld_hub_inst\|hub_tdo~359 2 COMB LC_X10_Y6_N4 1 " "Info: 2: + IC(1.298 ns) + CELL(0.442 ns) = 1.740 ns; Loc. = LC_X10_Y6_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~359'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "1.740 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.204 ns) + CELL(0.114 ns) 3.058 ns sld_hub:sld_hub_inst\|hub_tdo~360 3 COMB LC_X12_Y6_N0 1 " "Info: 3: + IC(1.204 ns) + CELL(0.114 ns) = 3.058 ns; Loc. = LC_X12_Y6_N0; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~360'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "1.318 ns" { sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.243 ns) + CELL(0.607 ns) 4.908 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X16_Y6_N5 0 " "Info: 4: + IC(1.243 ns) + CELL(0.607 ns) = 4.908 ns; Loc. = LC_X16_Y6_N5; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "1.850 ns" { sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.163 ns 23.70 % " "Info: Total cell delay = 1.163 ns ( 23.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.745 ns 76.30 % " "Info: Total interconnect delay = 3.745 ns ( 76.30 % )" {  } {  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "4.908 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.908 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.298ns 1.204ns 1.243ns } { 0.000ns 0.442ns 0.114ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.053 ns - Smallest " "Info: - Smallest clock skew is 0.053 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.272 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 127 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 127; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X16_Y6_N5 0 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X16_Y6_N5; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.49 % " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns 86.51 % " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.219 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.219 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 127 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 127; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.508 ns) + CELL(0.711 ns) 5.219 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] 2 REG LC_X10_Y5_N0 4 " "Info: 2: + IC(4.508 ns) + CELL(0.711 ns) = 5.219 ns; Loc. = LC_X10_Y5_N0; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]'" {  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "5.219 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.62 % " "Info: Total cell delay = 0.711 ns ( 13.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.508 ns 86.38 % " "Info: Total interconnect delay = 4.508 ns ( 86.38 % )" {  } {  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "5.219 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.219 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } { 0.000ns 4.508ns } { 0.000ns 0.711ns } } }  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "5.219 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.219 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } { 0.000ns 4.508ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "4.908 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.908 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] sld_hub:sld_hub_inst|hub_tdo~359 sld_hub:sld_hub_inst|hub_tdo~360 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.298ns 1.204ns 1.243ns } { 0.000ns 0.442ns 0.114ns 0.607ns } } } { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } { "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" "" { Report "E:/EDA/DDS/cosx/db/SINGT_cmp.qrpt" Compiler "SINGT" "UNKNOWN" "V1" "E:/EDA/DDS/cosx/db/SINGT.quartus_db" { Floorplan "E:/EDA/DDS/cosx/" "" "5.219 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.219 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } { 0.000ns 4.508ns } { 0.000ns 0.711ns } } }  } 0}